Fabric Die Interconnect Columns for Low-Latency Modular IC Links
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Solution Overview
Problem
Modern integrated circuit devices face challenges with limited reach and high latency in fabric die-to-fabric die interconnects due to peripheral interconnects, leading to routing congestion and reduced device performance.
Innovation Solution
Implementing a direct fabric die-to-fabric die interconnect interface, such as the Advanced Interface Bus-Direct (AIB-D), distributed across multiple columns within the programmable logic fabric, which communicates through silicon interposers, reducing reliance on traditional horizontal and vertical input/output interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral interconnects (HIO/VIO) are used for fabric die-to-fabric die communication, then device functionality is achieved, but routing congestion occurs at the fabric die shoreline and latency increases
Solution Approach 1:
The interconnect interface is segmented into multiple distributed columns throughout the fabric die, rather than being concentrated at the periphery. This segmentation allows multiple parallel communication paths, reducing latency and preventing routing congestion at any single shoreline location.
Solution Approach 2:
The interconnect interface transitions from a two-dimensional peripheral arrangement (HIO/VIO at shorelines) to a three-dimensional distributed structure with columns extending through the fabric die. This dimensional change enables direct vertical and horizontal connectivity, eliminating the need for data to travel to the periphery and reducing latency.
2Reliability
If peripheral interconnects are used for fabric die-to-fabric die communication, then device functionality is achieved, but routing congestion occurs at the fabric die shoreline
Solution Approach 1:
The interconnect interface is divided into multiple distributed columns throughout the fabric die, creating multiple independent communication channels. This segmentation distributes the routing load across the entire die area, eliminating concentration of traffic at the periphery and reducing routing congestion.
Solution Approach 2:
Interconnect columns are distributed locally throughout the fabric die rather than being concentrated at the periphery. Each local region has direct access to interconnect resources, reducing the need for long-distance routing and minimizing congestion at shoreline locations.
3Adaptability or versatility
If horizontal and vertical input/output interfaces are used, then fabric die connectivity is achieved, but the number of interfaces is limited by finite shorelines
Solution Approach 1:
The interconnect interface extends from the two-dimensional peripheral shoreline into the third dimension by distributing columns throughout the fabric die interior. This enables many more interface locations without increasing shoreline complexity, as interfaces are now available at multiple positions across the die area.
Solution Approach 2:
The distributed interconnect columns provide universal connectivity throughout the fabric die, allowing any region to access interconnect resources directly. This multi-functional approach replaces the specialized peripheral interface model, enabling versatile communication paths without being constrained by shoreline limitations.
Data Source
AI summary
The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.