Fabric Die Interconnect Layout for Low-Latency Modular IC Links
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Solution Overview
Problem
In modularized integrated circuit systems, the limited reach and number of horizontal and vertical input/output interfaces lead to routing congestion and high latency in fabric die-to-fabric die interconnects, reducing device performance and silicon yield.
Innovation Solution
The implementation of a direct fabric die-to-fabric die interconnect interface, such as an Advanced Interface Bus-Direct (AIB-D) interface, disposed in rows or sets of programmable logic fabric, which communicatively couples via a silicon interposer, enabling low latency connections and reducing routing congestion by distributing interconnect interfaces throughout the fabric die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral interconnects are used for fabric die-to-fabric die communication, then connectivity between dies is achieved, but routing congestion occurs at the fabric die shoreline and latency increases
Solution Approach 1:
The interconnect interface is segmented from the peripheral shoreline location and integrated directly into the fabric die core, dividing the communication path into direct fabric-to-fabric connections rather than routing through peripheral interfaces. This segmentation eliminates the bottleneck at the shoreline by creating dedicated interconnect pathways within the fabric structure itself.
Solution Approach 2:
The interconnect interface is moved from the two-dimensional peripheral shoreline to the three-dimensional interior of the fabric die, allowing vertical and horizontal integration within the fabric layers. This dimensional transition enables direct coupling between fabric dies without requiring shoreline routing, thereby reducing congestion and latency.
2Reliability
If peripheral interconnects are used for fabric die-to-fabric die communication, then connectivity between dies is achieved, but the number of available interfaces is limited by finite shorelines
Solution Approach 1:
The interconnect capability is segmented and distributed throughout the fabric die rather than concentrated at the periphery. Multiple interconnect interfaces can be instantiated at different locations within the fabric, increasing the total number of available interfaces beyond the constraints of shoreline length.
Solution Approach 2:
The fabric die structure itself is given dual functionality: it serves both as the logic fabric and as the interconnect medium. This universality allows any location within the fabric to potentially host an interconnect interface, making the system adaptable to varying connectivity requirements without being constrained by fixed peripheral interface locations.
3Reliability
If peripheral interconnects are used for fabric die-to-fabric die communication, then connectivity is established, but excess routing circuitry is consumed
Solution Approach 1:
The interconnect function is merged with the fabric die structure itself, eliminating the need for separate peripheral routing circuitry. By integrating the interconnect interface directly into the fabric, the same physical structures serve both logic and interconnect purposes, thereby reducing overall routing circuitry consumption.
Solution Approach 2:
The interconnect interface is extracted from the peripheral routing domain and placed directly within the fabric die core. This extraction removes the requirement for long-distance peripheral routing paths, thereby eliminating the consumption of excess routing circuitry that would otherwise be needed to connect distant shoreline interfaces.
4Reliability
If peripheral interconnects are used for fabric die-to-fabric die communication, then connectivity is achieved, but device performance is reduced due to high latency
Solution Approach 1:
The interconnect interface is prepared and integrated within the fabric die structure during manufacturing, establishing direct communication pathways in advance. This preliminary integration eliminates the need for complex routing operations during operation, thereby reducing communication latency between fabric dies.
Solution Approach 2:
Data transmission is accelerated by skipping the intermediate peripheral routing step. The direct fabric-to-fabric interconnect allows data to rush through the interface without being funneled through the congested shoreline routing, thereby significantly reducing transmission latency and improving overall device performance.
Data Source
AI summary
The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.