Early Fabric Error Forwarding for SoC Reliability
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Solution Overview
Problem
The integration of diverse intellectual property blocks into a single System-on-Chip (SoC) is complex due to varying requirements and design uniqueness, leading to slow error recognition and difficulty in tracing hardware errors back to their origin, as errors must propagate through multiple layers of hardware and software before becoming visible.
Innovation Solution
Implementing an Integrated On-Chip System Fabric (IOSF) specification that standardizes an interconnect protocol for attaching IP blocks within a chip, enabling efficient design of various types of chips and facilitating error message processing through a fabric-based system that forwards error messages close to the time of occurrence, allowing for quicker error analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If errors propagate through multiple layers of hardware and software before becoming visible, then system reliability is maintained through proper error handling, but error recognition time increases and error origin tracing becomes difficult
Solution Approach 1:
The patent implements preliminary action by capturing error information at the point of occurrence and forwarding it through the fabric immediately. Error agents are positioned to detect and forward errors before they propagate through multiple system layers, preserving the original error context and location information for rapid analysis while maintaining system reliability through proper error handling protocols.
2Adaptability or versatility
If diverse IP blocks are integrated into a single SoC, then device functionality and versatility are improved, but design complexity increases due to varying requirements and design uniqueness
Solution Approach 1:
The patent applies universality by implementing a standardized fabric interface and common error handling protocol that all diverse IP blocks must adhere to. This universal framework allows different functional blocks (graphics, display, security, PCIe) to be integrated into a single SoC without requiring custom integration logic for each block, thereby managing design complexity while maintaining versatility.
Solution Approach 2:
The fabric serves as an intermediary layer between diverse IP blocks and the system level. Error agents embedded within the fabric act as mediators that intercept errors from any IP block and forward them through the standardized error handling path, eliminating the need for complex point-to-point error handling connections between each IP block pair.
3Adaptability or versatility
If IP blocks are re-designed to accommodate interface and signaling requirements of a given SoC, then integration compatibility is improved, but design time and development cost increase
Solution Approach 1:
The standardized fabric interface and error handling protocol are defined and established before IP block integration. This preliminary standardization allows IP blocks to be designed once with predefined interface requirements, eliminating the need for repeated redesigns for different SoC configurations and reducing overall design time.
Data Source
AI summary
An embodiment includes a processor, included in a first die, detecting a first hardware error (e.g., memory corruption error). The processor formulates a first error message based on the detected first error. The processor may forward the first error message, via a first fabric included on the first die, to a first intellectual property (IP) agent or block, also included in the first die. This may be done using an in-band message, such as one that adheres to the integrated on-chip system fabric (IOSF) specification. The first IP agent may issue an error message that may, for example, alert a user to the error in a manner that is relatively close in time when the error first occurs. This may facilitate better error analysis. The first IP agent may include a processor (e.g., graphics processor), controller (e.g., power management controller), and the like. Other embodiments are described herein.