Communication Fabric Latency Synchronization for SoC Memory Controllers
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Solution Overview
Problem
In complex Systems on Chips (SoCs), the split topology used for data and control links in communication fabrics leads to unequal latencies, causing write commands to arrive at memory controllers before write data, resulting in reduced performance due to idle clock cycles when no data is available for servicing.
Innovation Solution
Implementing a mechanism within the communication fabric's clusters to synchronize write commands and data, where the controller marks the write command as a candidate only when the write data is determined to arrive ahead of the command, using combinatorial logic and sequential elements to manage upstream and downstream links, ensuring data and control resources are used efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a split topology is used to separate data links from control links, then data bus utilization through the fabric is improved, but the latencies through the control path and data path become unequal
Solution Approach 1:
The patent applies preliminary action by having intermediate clusters determine and signal the arrival time of write data before the write command reaches the memory controller. This allows the memory controller to know in advance whether write data will arrive ahead of the write command, enabling it to avoid selecting commands that would result in idle clock cycles. The determination of data arrival timing is performed in advance at intermediate clusters, preventing the latency inequality problem from causing performance degradation.
2Speed
If write command is selected for servicing by memory controller before write data arrives, then command processing speed is improved, but performance reduces due to idle clock cycles when no data is available
Solution Approach 1:
The patent implements feedback by having intermediate clusters monitor and signal the status of write data transmission back to the memory controller. The memory controller receives feedback about whether write data has been issued and is expected to arrive ahead of the write command. This feedback mechanism allows the memory controller to make informed decisions about command selection, avoiding the selection of commands that would lead to idle clock cycles and performance degradation.
3Productivity
If write command and write data are sent at the same time on separate links, then data bus utilization is improved, but write command arrives at memory controller sooner than write data
Solution Approach 1:
The patent applies preliminary action by having intermediate clusters determine the expected arrival time of write data before the write command reaches the memory controller. This preliminary determination allows the memory controller to anticipate whether write data will arrive ahead of the write command, even though they were sent simultaneously on separate links. The intermediate clusters perform the prediction in advance, enabling the memory controller to adjust its command selection strategy accordingly.
Data Source
AI summary
A system and method for efficiently routing data in a communication fabric. A computing system includes a fabric for routing data among one or more agents and a memory controller for system memory. The fabric includes multiple hierarchical clusters with a split topology where the data links are physically separated from the control links. A given cluster receives a write command and associated write data, and stores them in respective buffers. The given cluster marks the write command as a candidate to be issued to the memory controller when it is determined the write data will arrive ahead of the write command at the memory controller after being issued. The given cluster prevents the write command from becoming a candidate to be issued when it is determined the write data may not arrive ahead of the write command at the memory controller.