Fabry-Perot Interference Filter Wafer Etching for Yield Stability
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Solution Overview
Problem
The manufacturing of Fabry-Perot interference filters faces challenges in improving both efficiency and yield due to the complexity of the fine structure involved.
Innovation Solution
A method involving the formation of mirror layers, sacrificial layers, and stress adjustment layers on a wafer, followed by simultaneous etching and laser-assisted cutting to efficiently form gaps and reduce in-plane stress, thereby enhancing manufacturing efficiency and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the removing step is carried out individually at a chip level, then the manufacturing process can be simpler, but the manufacturing efficiency is significantly reduced
Solution Approach 1:
The patent merges multiple individual chip-level removing steps into a single wafer-level removing step. By performing the removal process on the entire wafer simultaneously rather than on each chip separately, the manufacturing efficiency is dramatically improved while the process remains manageable through proper tooling and fixture design
2Productivity
If the removing step is carried out at a wafer level, then the manufacturing efficiency is improved, but the in-plane stress bias increases causing yield reduction
Solution Approach 1:
The patent segments the wafer into multiple regions with different removing step conditions. By dividing the wafer processing into distinct zones with tailored etching parameters, the in-plane stress bias is reduced while maintaining the efficiency benefits of wafer-level processing. This segmentation allows different areas to be optimized for their specific requirements
3Ease of manufacture
If cutting is performed without forming thinned regions in advance, then the process is simpler, but external forces damage the gap structure
Solution Approach 1:
The patent performs preliminary thinning of the wafer at the cutting lines before the actual cutting operation. By pre-thinning the regions where cuts will be made, the structural integrity of the gap is protected during cutting, reducing damage while the overall process remains straightforward through integrated thinning and cutting steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the efficient formation of gaps between mirror layers, reduces stress-related damage, and improves the yield and stability of the Fabry-Perot interference filters, enabling high-quality mass production.
Implementation Method 1
a removing step of simultaneously removing the plurality of two-dimensionally arranged portions expected to be removed from the sacrificial layer through etching after the forming step
Implementation Method 2
a cutting step of cutting the wafer into the plurality of substrates along each of the plurality of lines after the removing step
Implementation Method 3
forming a modified region within the wafer along each of the plurality of lines through irradiation of laser light and extending a crack in a thickness direction of the wafer from the modified region
Data Source
AI summary
A method of manufacturing a Fabry-Perot interference filter includes a forming step of forming a first mirror layer having a plurality of first mirror portions, a sacrificial layer having a plurality of portions expected to be removed, and a second mirror layer having a plurality of second mirror portions on a first main surface of a wafer which includes parts corresponding to a plurality of two-dimensionally arranged substrates and is expected to be cut into the plurality of substrates along each of a plurality of lines; a removing step of simultaneously removing the plurality of two-dimensionally arranged portions expected to be removed from the sacrificial layer through etching after the Ruining step; and a cutting step of cutting the wafer into the plurality of substrates along each of the plurality of lines after the removing step.


