Fabry-Perot Interference Filter Wafer Etching for Yield-Stable Gap Formation
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Solution Overview
Problem
The manufacturing of Fabry-Perot interference filters faces challenges in improving both efficiency and yield due to the complexity and fragility of the fine structures involved.
Innovation Solution
A method is developed where the sacrificial layer is etched at the wafer level, forming gaps between mirror portions efficiently, and thinned regions are created to reduce stress and prevent damage during the cutting process, using laser light and expanding tape to minimize external forces and particle infiltration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the removing step is carried out individually at chip level, then manufacturing precision can be maintained, but manufacturing efficiency deteriorates
Solution Approach 1:
The patent merges multiple individual chip processing operations into a single wafer-level etching process. The etching step that removes portions of the sacrificial layer is performed across the entire wafer simultaneously, treating multiple chips as one unified processing unit. This combining approach maintains precision through uniform wafer-level control while dramatically improving efficiency by processing many chips in parallel rather than sequentially.
Solution Approach 2:
The patent transitions from one-dimensional sequential chip-by-chip processing to two-dimensional parallel wafer-level processing. By etching the sacrificial layer across the entire wafer surface simultaneously, the process exploits the two-dimensional arrangement of multiple chips on the wafer to perform parallel operations, thereby increasing throughput while maintaining the precision required for gap formation.
2Productivity
If etching is carried out at wafer level, then manufacturing efficiency is improved, but stress bias in the wafer increases
Solution Approach 1:
The patent applies local quality by performing etching at multiple predetermined locations across the wafer rather than attempting to etch the entire wafer uniformly in a single step. This distributed approach allows different regions of the wafer to be processed with locally optimized parameters, reducing cumulative stress bias while maintaining the efficiency benefits of wafer-level processing. The etching is carried out at a first location, then the wafer is repositioned to etch at a second location, and so on.
Solution Approach 2:
The patent employs periodic action by dividing the wafer-level etching process into multiple sequential etching steps at different locations. The wafer is etched at a first predetermined location, then repositioned and etched at a second predetermined location, continuing this periodic sequence across multiple locations. This periodic approach distributes the stress accumulation over time and space, preventing excessive stress bias while maintaining overall processing efficiency.
3Device complexity
If the wafer is cut into substrates without thinned regions, then manufacturing process is simpler, but the structure around the gap is damaged
Solution Approach 1:
The patent applies preliminary action by creating thinned regions in the substrate at predetermined locations before the cutting step. These thinned regions are formed by selectively removing material where the cuts will eventually be made. By preparing these weakened zones in advance, the subsequent cutting process can proceed without exerting excessive force on the intact substrate, thereby preventing damage to the delicate gap structures while adding only a minimal extra step to the manufacturing process.
4Ease of manufacture
If conventional manufacturing methods are used, then process simplicity is maintained, but yield deteriorates
Solution Approach 1:
The patent combines multiple individual chip processing operations into unified wafer-level processes for both etching and cutting. By merging the etching of multiple chips into a single wafer-level operation and combining the cutting of multiple substrates into a coordinated wafer-level process, the manufacturing workflow is simplified into fewer, more efficient steps. This merging approach improves yield by ensuring uniform processing across all chips while maintaining relative process simplicity through standardized wafer-level procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances manufacturing efficiency and yield by reducing in-plane stress bias and preventing damage to the structure around the gap, allowing for the production of high-quality Fabry-Perot interference filters with improved stability and reduced contamination.
Implementation Method 1
the removing step of removing the plurality of portions expected to be removed from the sacrificial layer through etching
Implementation Method 2
using laser light and expanding tape to minimize external forces and particle infiltration
Data Source
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AI summary
A method of manufacturing a Fabry-Perot interference filter includes a forming step of forming a first mirror layer having a plurality of first mirror portions, a sacrificial layer having a plurality of portions expected to be removed, and a second mirror layer having a plurality of second mirror portions on a first main surface of a wafer which includes parts corresponding to a plurality of two-dimensionally arranged substrates and is expected to be cut into the plurality of substrates along each of a plurality of lines; a removing step of simultaneously removing the plurality of two-dimensionally arranged portions expected to be removed from the sacrificial layer through etching after the forming step; and a cutting step of cutting the wafer into the plurality of substrates along each of the plurality of lines after the removing step.