Face-to-Back Hybrid Bonding Without Dual Carrier Support
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Solution Overview
Problem
Current die-to-wafer bonding processes are limited by the use of dual carrier paradigms, which increase cycle time, cost, and can adversely affect yield, especially when working with thinner and more fragile dies.
Innovation Solution
A face-to-back (F2B) die-to-wafer (D2W) hybrid bonding paradigm is introduced, where the carrier wafer supporting the top die is eliminated, allowing for direct bonding of the top and bottom dies in a face-to-back configuration, thereby reducing thermal resistance and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If dual carrier paradigm is used to support top and bottom dies, then manufacturing stability is improved, but cycle time increases and process costs increase
Solution Approach 1:
The patent extracts and eliminates one of the two carrier wafers from the bonding process. Specifically, the bottom carrier wafer is removed, allowing the bottom die to be directly bonded to the top wafer without requiring carrier support. This reduces the number of components and process steps while maintaining bonding stability through direct wafer-to-die contact.
Solution Approach 2:
The patent merges the functions of the bottom carrier wafer and bottom die into a single direct bonding operation. By eliminating the bottom carrier, the support function and the die function are combined, reducing cycle time and process complexity while maintaining manufacturing stability through direct bonding interfaces.
2Stability of the object's composition
If dual carrier paradigm is used to support top and bottom dies, then manufacturing stability is improved, but process costs increase
Solution Approach 1:
The patent extracts and eliminates one of the two carrier wafers from the bonding process. Specifically, the bottom carrier wafer is removed, allowing the bottom die to be directly bonded to the top wafer without requiring carrier support. This reduces the number of components and process steps while maintaining bonding stability through direct wafer-to-die contact.
Solution Approach 2:
The patent discards the bottom carrier wafer after the bonding process is complete. By eliminating the need for the bottom carrier, material costs and processing costs are reduced. The top wafer serves as the permanent substrate, while the bottom carrier is temporarily used only if needed and then removed, reducing overall process costs.
3Temperature
If carrier wafer is eliminated for direct bonding, then thermal resistance decreases and heat dissipation improves, but manufacturing complexity increases for thinner dies
Solution Approach 1:
The patent extracts and eliminates one of the two carrier wafers from the bonding process. Specifically, the bottom carrier wafer is removed, allowing the bottom die to be directly bonded to the top wafer without requiring carrier support. This reduces the number of components and process steps while maintaining bonding stability through direct wafer-to-die contact.
Solution Approach 2:
The patent changes the bonding parameters and process conditions to accommodate thinner dies without carrier support. By adjusting bonding pressure, temperature, and alignment precision, the process achieves successful bonding of fragile thin dies directly to the wafer, eliminating thermal resistance while managing the increased manufacturing complexity through optimized process parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach decreases cycle time and reduces process costs by eliminating unnecessary steps, while enhancing thermal performance and improving device performance through increased heat dissipation.
Implementation Method 1
electrical connections can be achieved during annealing via metal diffusion bonding
Implementation Method 2
Fusion bonding can include a plasma and/or thermal treatment
Implementation Method 3
Fusion bonding can include a plasma and/or thermal treatment
Data Source
AI summary
A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.