Face-to-Face Bonded Semiconductor Structure for Dense Capacitor Integration
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Solution Overview
Problem
The challenge is to further reduce the dimensions of semiconductor structures to meet the demands of miniaturization and thinness in electronic devices, while also simplifying the connection process and reducing the complexity of conductive routes between storage and control chips.
Innovation Solution
A semiconductor structure is formed by connecting a storage chip and a control chip in a face-to-face bonding manner, with a capacitor structure located on the surface of the storage chip, electrically connected to transistors, using a gate-all-around structure to increase capacitor density and reduce manufacturing difficulties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional bonding methods are used to connect storage chip and control chip, then the bonding process is simple, but the conductive routes become complex and production efficiency decreases
Solution Approach 1:
The patent transitions from traditional wire bonding (2D planar connection) to face-to-face bonding (3D vertical connection). The bonding pad on the storage chip bonds directly to the contact hole on the control chip, creating a vertical conductive path that simplifies the routing and reduces the number of conductive paths needed.
Solution Approach 2:
The invention divides the semiconductor structure into two separate chips (storage chip and control chip) that are bonded face-to-face. This segmentation allows each chip to be optimized independently while simplifying the overall conductive route structure through direct vertical bonding between corresponding pads and contact holes.
2Volume of moving object
If chip dimensions are reduced to meet miniaturization requirements, then the device size decreases, but the manufacturing precision requirements increase
Solution Approach 1:
By moving to face-to-face bonding in the vertical dimension, the patent reduces the lateral footprint of the device while concentrating precision requirements to a single bonding interface. The vertical bonding approach allows for smaller overall chip volume while maintaining manageable precision requirements through direct pad-to-contact-hole alignment.
Solution Approach 2:
The control chip is positioned face-to-face with the storage chip, with contact holes precisely aligned to bonding pads. This nested arrangement allows compact integration while the precise alignment of bonding pads with contact holes ensures manufacturing feasibility even at reduced dimensions.
3Quantity of substance
If capacitor density is increased to improve storage capacity, then the storage capacity increases, but the device complexity increases
Solution Approach 1:
The capacitor structure utilizes vertical stacking with gate-all-around configuration, moving from planar 2D capacitor layout to 3D vertical architecture. This allows increased capacitor density by stacking capacitors in the vertical dimension rather than spreading them out laterally, reducing overall device footprint while maintaining high storage capacity.
Solution Approach 2:
The capacitor employs a gate-all-around structure with multiple material layers including conductive gates, dielectric materials, and semiconductor substrates. This composite structure achieves high capacitor density through efficient use of vertical space while the systematic layering maintains manufacturing manageability.
Data Source
AI summary
A semiconductor structure includes a storage chip, a control chip, and a capacitor structure. The storage chip includes an array area. The control chip includes a peripheral area. The control chip and the storage chip are connected in a face-to-face bonding manner. The capacitor structure is located on a surface, away from a bonding surface, of the storage chip. The capacitor structure includes capacitors electrically connected to corresponding transistors in the array area.