Face-to-Face Die Structure With TSV Interconnects for Fewer Pin Holes
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating smaller electronic components due to the need for smaller and more creative packaging techniques, particularly in forming die structures that reduce pin hole defects and improve yield and reliability.
Innovation Solution
The formation of die structures involves bonding integrated circuit dies face-to-face with through-substrate vias (TSVs) and a back-side interconnect structure, omitting the recessing of the semiconductor substrate, which reduces pin hole defects by using an additional layer of conductive vias and employing a nitride-oxide-nitride-oxide (NONO) structure for gap-fill dielectric to avoid cracking and etching issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional die bonding techniques are used, then integration density can be improved, but pin hole defects increase and yield decreases
Solution Approach 1:
The patent divides the bonding interface into multiple functional layers including a first dielectric layer, a second dielectric layer, and an interconnect structure with conductive vias. This segmentation allows each layer to perform its specific function (electrical connection, mechanical support, insulation) independently, reducing the occurrence of pin hole defects while maintaining high integration density through face-to-face bonding of multiple dies.
2Ease of manufacture
If semiconductor substrate recessing is performed, then die structure formation is enabled, but manufacturing complexity and potential defects increase
Solution Approach 1:
Instead of recessing the semiconductor substrate to form the bonding interface, the patent inverts the approach by bonding dies face-to-face and then forming dielectric layers and conductive vias on the bonding interface. This eliminates the complex substrate recessing process while achieving the same die structure formation, thereby reducing manufacturing complexity and potential defects associated with substrate handling.
3Volume of moving object
If smaller packaging techniques are implemented, then device size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional face-to-face bonding of multiple dies, stacking them vertically to achieve higher integration density in a smaller footprint. This dimensional change allows compact device sizing without requiring proportional reductions in feature sizes, as the scaling benefit comes from the vertical stacking architecture rather than lateral feature shrinkage.
Data Source
AI summary
Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.