Face-down Microelectronic Package Assembly via Wafer Positioning
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Solution Overview
Problem
Current methods for manufacturing multi-chip microelectronic packages face challenges in combining microelectronic elements from the same wafer due to different orientations and contact patterns, leading to poor compound speed bin yield and inefficient assembly processes.
Innovation Solution
A method where microelectronic elements are attached to a substrate with aligned openings for forming electrical connections, allowing elements from the same wafer to be assembled together, maximizing compound speed bin yield by transferring them from closely neighboring positions on a single diced wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microelectronic elements are assembled in different orientations (face-down and face-up) to accommodate contact patterns, then the assembly process can proceed with existing manufacturing methods, but the compound speed bin yield deteriorates because elements from the same wafer cannot be combined
Solution Approach 1:
The patent inverts the conventional assembly approach by placing both microelectronic elements in face-down orientation on the substrate, rather than using face-up for one element. This inversion allows contact alignment through openings in the substrate for both elements, enabling them to be transferred from neighboring positions on the same wafer while maintaining proper electrical connections.
Solution Approach 2:
The substrate is designed with multiple openings that can accommodate contacts from multiple elements in face-down orientation. This universal design allows the same substrate structure to handle both elements uniformly, eliminating the need for different orientations and enabling high-volume manufacturing of multi-chip packages from the same wafer.
2Reliability
If microelectronic elements are transferred from neighboring positions on a single diced wafer, then the compound speed bin yield is maximized by ensuring consistent performance, but the manufacturing precision requirements increase due to alignment constraints
Solution Approach 1:
The substrate openings are pre-configured at known positions before element placement. This preliminary arrangement of openings allows for systematic alignment of elements from neighboring wafer positions, reducing the precision burden during the actual transfer process since the target locations are already defined and spaced to accommodate standard wafer neighboring positions.
3Productivity
If all microelectronic elements are processed in face-down orientation on the substrate, then high volume manufacturing efficiency is improved by simplifying the assembly sequence, but the device complexity increases due to the need for through-substrate openings and alignment structures
Solution Approach 1:
The substrate is segmented with multiple discrete openings, each dedicated to receiving contacts from specific element positions. This segmentation allows each opening to be independently aligned with corresponding contacts, simplifying the overall alignment process while enabling efficient high-volume manufacturing of multi-chip packages from the same wafer.
Data Source
AI summary
In a high volume method for manufacturing a microelectronic package, a spacer element and a first die, i.e., microelectronic element, can be attached face-down to a surface of a substrate, contacts on the first die facing a first through opening of the substrate. Then, a second die can be attached face-down atop the first die and the spacer element, contacts on the second die disposed beyond an edge of the first die and facing a second through opening in the substrate. Electrical connections can then be formed between each of the first and second dies and the substrate. The first and second dies can be transferred from positions of a single diced wafer which are selected to maximize compound speed bin yield of the microelectronic package.