Face-Down Stacked Die Assembly with Peripheral Terminals
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Solution Overview
Problem
Current microelectronic assemblies with stacked semiconductor chips face challenges in reducing the overall size and height, particularly when chips have contacts located in central regions, limiting the compactness and efficiency of multi-chip packages.
Innovation Solution
A microelectronic assembly design featuring a substrate with specific openings and peripheral regions that allow for the stacking of microelectronic elements with bond pads aligned to these openings, enabling efficient electrical connections and reduced size through the use of conductive elements and wire bonds, while allowing for encapsulant flow and terminal placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are mounted side-by-side on a single package substrate, then the chips can be interconnected and mounted to the circuit panel, but the aggregate area occupied on the circuit panel is greater than the total surface area of the individual chips
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side chip arrangement to a three-dimensional stacked arrangement. Multiple chips are vertically stacked on the package substrate, with chips positioned at different heights (first chip at first height, second chip at second height). This vertical stacking enables interconnection between chips through conductors extending between different levels, while significantly reducing the horizontal area occupied on the circuit panel compared to flat mounting arrangements.
2Area of stationary object
If chips are stacked one on top of another, then the area of the circuit panel is reduced, but the overall height or dimension perpendicular to the plane of the circuit panel increases
Solution Approach 1:
The patent implements a nested structure where multiple chips are vertically stacked within a compact package substrate. The first chip is positioned at a first height and the second chip at a second height, with both chips contained within the vertical envelope of the package substrate. This nesting approach allows the chips to be integrated in a space-efficient manner, reducing the horizontal footprint while managing the vertical dimension through the package substrate's height.
3Adaptability or versatility
If chips have contacts located in central regions, then the chip design is optimized for certain applications, but the stacking and compactness of multi-chip packages is limited
Solution Approach 1:
The patent introduces a package substrate as an intermediary structure that facilitates the interconnection of chips with centrally-located contacts. The substrate provides conductor pathways that extend between chips at different heights, enabling electrical connection between the central contacts of stacked chips. This intermediary substrate manages the complexity of interconnecting chips with non-peripheral contacts by providing routed conductors that bridge the vertical spacing between chips.
Data Source
AI summary
A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region.