Face-to-Face 3D IC Shared Power Distribution Network

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Solution Overview

Problem

Conventional 3D integrated circuits face challenges in efficiently sharing power distribution networks between chips fabricated using different processes, often resulting in imperfect alignments and defects at connection interfaces, which can lead to local voltage drops and increased fabrication costs.

Innovation Solution

Implementing a shared power distribution network between two face-to-face positioned chips, where the highest metallization levels of one chip form a common power distribution grid connected via a three-dimensional interconnect network, simplifying the fabrication process and reducing costs by eliminating the need for separate power distribution networks in the highest metallization levels of both chips.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If separate power distribution networks are implemented in the highest metallization levels of both chips, then each chip can be designed independently with conventional 2D design processes, but this increases device complexity and fabrication costs

Engineering Contradiction:

Improveindependence of chip design processesVSAvoidcomplexity of power distribution networks

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the power distribution networks of two separate chips by making the highest metallization levels electrically connected through face-to-face joining. This allows a single power distribution network to serve both chips, reducing overall complexity while maintaining design independence through separate lower metallization levels.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The highest metallization levels of both chips are designed to serve dual functions: as interconnect layers for signal transmission and as a shared power distribution network. This multi-functionality eliminates the need for separate power distribution structures in each chip.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If separate power distribution networks are implemented in both chips, then each chip maintains its own power supply architecture, but this leads to increased fabrication costs and structural complexity

Engineering Contradiction:

Improveindependence of power supply architecturesVSAvoidfabrication costs

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines the power distribution functions of two independent chips into a single shared network through electrical connection of the highest metallization levels. This merging reduces fabrication costs by eliminating redundant power distribution structures while maintaining reliable power supply through the unified network.

Inventive Principle:

Principle #5Merging (Combining)

3Adaptability or versatility

If conventional face-to-face joining is used with separate power distribution networks, then chip design independence is maintained, but imperfect alignment and defects occur at connection interfaces causing local voltage drops

Engineering Contradiction:

Improvedesign independence of chipsVSAvoidalignment precision at connection interfaces

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

By merging the power distribution networks through electrical connection of highest metallization levels, the patent creates a unified power supply system that is less sensitive to alignment imperfections. The larger effective connection area and distributed power delivery reduce the impact of local misalignments on voltage stability.

Inventive Principle:

Principle #5Merging (Combining)

4Adaptability or versatility

If separate power distribution networks are used in both chips, then each chip can be optimized for its specific function, but this increases the overall device complexity and power distribution infrastructure

Engineering Contradiction:

Improvefunctional optimization of each chipVSAvoidoverall power distribution infrastructure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the power distribution infrastructure of two functionally optimized chips into a single shared network. The highest metallization levels serve both as interconnects for functional signals and as power distribution pathways, reducing overall infrastructure complexity while preserving functional optimization through separate lower metallization levels.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The highest metallization levels are designed with multi-functionality, serving both as signal interconnects for chip-specific functions and as power distribution network elements. This universal design reduces the need for separate dedicated power distribution structures in each chip.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10777537B2Face-to-face three-dimensional integrated circuit of simplified structure

Publication Date: 2020.09.15 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

AI summary

An integrated circuit including a first chip including a stack of a substrate, of an active layer and of interconnect layers; a second chip including a stack of a substrate, of an active layer and of interconnect layers; an interconnect network for interconnecting the first and second chips. The interconnect layer of the highest metallization level of the first chip includes a power distribution network; the interconnect layer of the highest metallization level of the second chip is without a power distribution network.