Face-to-Face Chip Interconnection for High Bandwidth
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Solution Overview
Problem
Chip stacking methods face limitations in interconnections through the common chip, particularly due to corner crossing densities and challenging power delivery oriented vertically along the vertical lengths of multiple chips.
Innovation Solution
The packaging structure involves direct electrical connections between active surfaces of first and second chips in a face-to-face arrangement, oriented transversely with respect to a common chip, using conductive elements like microbumps or microjoins, and corner crossings to enhance bandwidth and power delivery, while also using a carrier chip with through-silicon vias and 'T' connectors for additional connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chip stacking methods are used to increase system performance, then the number of interconnected chips increases, but the interconnections through the common chip are limited by corner crossing densities
Solution Approach 1:
The patent transitions from vertical interconnections through a common chip to face-to-face active surface connections between chips. This dimensional change eliminates the bottleneck of corner crossing densities by establishing direct lateral connections between multiple chips, allowing more chips to be interconnected without increasing complexity through the common chip.
Solution Approach 2:
The patent segments the interconnection architecture by removing the single common chip bottleneck and creating multiple independent face-to-face connection paths between chips. This segmentation distributes the interconnection load across multiple direct links, reducing the complexity concentrated in the common chip's corner crossings.
2Power
If power delivery is oriented vertically along the vertical lengths of multiple chips, then power can be delivered to the common chip, but the power delivery becomes challenging
Solution Approach 1:
The patent changes the power delivery orientation from vertical (through the common chip) to lateral (between active surfaces of directly connected chips). This dimensional shift enables more efficient power distribution by utilizing the face-to-face connection paths, reducing the complexity of vertical power delivery through the common chip.
3Quantity of substance
If direct electrical connections are made between active surfaces of first and second chips, then the number of connections increases and active area for interconnection is doubled, but the structural complexity increases
Solution Approach 1:
The face-to-face active surface connections serve multiple functions simultaneously: they provide signal interconnections, power delivery paths, and mechanical support between chips. This multi-functionality increases the number of connections while managing structural complexity by consolidating multiple functions into a single connection architecture.
Solution Approach 2:
The patent merges the functions of signal transmission and power delivery into the same face-to-face active surface connections. By combining these functions, the structure achieves higher connection density without proportionally increasing complexity, as the same physical interface handles multiple tasks.
4Quantity of substance
If corner crossings are used to connect chips to the common chip, then interconnections can be established, but the corner crossing densities limit the number of interconnections
Solution Approach 1:
The patent eliminates corner crossing constraints by transitioning from vertical connections through the common chip to lateral face-to-face connections between active surfaces. This dimensional change removes the manufacturing precision bottleneck associated with high-density corner crossings, enabling more interconnections without proportionally increasing manufacturing difficulty.
Data Source
AI summary
A packaging structure is provided. The packaging structure includes first and second chips, at least one surface of each of the first and second chips being an active surface and a common chip to which at least one of the first and second chips is electrically interconnected. The respective active surfaces of the first and second chips are directly electrically interconnected to one another in a face-to-face arrangement and are oriented transversely with respect to the common chip.