Face-to-Face Die Stack Assembly for Yield-Stable 3D Packaging
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Solution Overview
Problem
Semiconductor die stacking faces challenges in maintaining thermal and mechanical stability while being thin, with increased complexity and cost due to the risk of a single defective die affecting the entire stack, leading to yield losses and higher costs as the number of dies increases.
Innovation Solution
The approach involves creating semiconductor device assemblies with face-to-face subassemblies, where each die stack is separated and encapsulated, with interconnect structures providing both electrical connections and structural stability, allowing for modularization and reducing the impact of a defective die by arranging dies into two separate stacks with conductive pillars surrounded by dielectric material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple dies are stacked together to increase functionality, then the device capabilities are improved, but the risk of defective dies increases and yield decreases
Solution Approach 1:
The patent divides the semiconductor package into multiple independent die stacks, where each stack contains a subset of dies. This segmentation ensures that a defect in one die does not propagate to other stacks, thereby maintaining yield while increasing overall device capabilities through the combination of multiple functional stacks.
2Adaptability or versatility
If the number of dies in the stack is increased to enhance functionality, then device capabilities are improved, but thermal and mechanical stability become difficult to maintain
Solution Approach 1:
The patent segments the dies into multiple smaller stacks rather than creating one large stack. This reduces the thermal and mechanical stress concentration in each individual stack, making it easier to maintain stability while still achieving enhanced functionality through the combination of multiple stacks within the package.
Solution Approach 2:
The patent transitions from a single vertical stack configuration to a multi-stack arrangement that utilizes horizontal spatial distribution. This dimensional change allows thermal and mechanical loads to be distributed across multiple independent structures, improving overall stability while maintaining enhanced device capabilities.
3Area of stationary object
If conventional die stacking is used to reduce package size, then a compact footprint is achieved, but the complexity and cost increase due to defect risk
Solution Approach 1:
The patent employs segmented die stacks arranged in a multi-stack configuration that achieves compact footprint similar to conventional stacking. However, the segmentation reduces complexity and cost by isolating defects to individual stacks, thereby improving yield and reducing the impact of defects on overall device functionality.
4Reliability
If a single defective die is present in the stack, then the entire stack is affected, but modularization could reduce this impact
Solution Approach 1:
The patent implements modularization by dividing dies into independent stacks, where each stack functions as a separate module. This segmentation limits the impact of a defective die to its specific stack, preventing failure propagation to other stacks. The modular design achieves improved reliability while managing complexity through standardized stack configurations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the reliability and yield of semiconductor device assemblies by reducing the risk of defective dies, maintaining a compact footprint, and providing stable thermal and mechanical performance, thus addressing the drawbacks of conventional die stacking.
Implementation Method 1
conductive pillars surrounded by dielectric material
Data Source
AI summary
A semiconductor device assembly having face-to-face subassemblies is provided. The assembly includes a first and second semiconductor device subassembly. Both subassemblies include a substrate, a stack of semiconductor dies, and an interconnect structure. The interconnect structures include a conductive pillar surrounded by dielectric material. Both substrates form opposing outer sides of the assembly, while the interconnect structures are disposed on the inside surface of their respective substrates and are directly coupled to one another. The die stacks are shorter than their respective interconnect structures, and therefore can also be disposed on the inside surface of their respective substrates. An encapsulant material—comprising a different material than the dielectric material—at least partially encapsulates the stacks and the interconnect structures.