Face-to-Face Inductor Void for Parasitic Capacitance Reduction
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Solution Overview
Problem
Forming semiconductor devices from multiple dies poses challenges such as high connection resistance, interference between components, and reduced yields due to power delivery issues and parasitic capacitance, especially in face-to-face die arrangements where inductors have not been effectively used.
Innovation Solution
Incorporating a void, such as an air gap, between inductors and adjacent dies to reduce parasitic capacitance, and using Through Silicon Vias (TSVs) to enhance power delivery by extending them through metallization layers for improved electrical and mechanical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If inductors are formed over the semiconductor substrate in face-to-face die arrangement, then high speed clock operation and power filtering are enabled, but parasitic capacitance from adjacent die degrades inductor performance
Solution Approach 1:
The patent extracts the harmful dielectric material from the region between the inductor and adjacent die by forming a void. This removes the source of parasitic capacitance while preserving the inductor's position and functionality for high speed clock operation and power filtering
Solution Approach 2:
The patent introduces an inert air environment (void) between the inductor and adjacent die. This inert atmosphere replaces the harmful dielectric material, creating an environment that does not contribute to parasitic capacitance while allowing the inductor to maintain its electrical performance
2Quantity of substance
If multiple semiconductor dies are connected face-to-face, then interconnect density is increased, but connection resistance and power delivery issues increase
Solution Approach 1:
The patent extends TSVs through multiple metallization layers to create vertical power delivery paths in the third dimension. This dimensional approach allows power to be delivered through multiple levels, reducing resistance while maintaining high interconnect density in the horizontal plane
3Reliability
If TSVs are extended through metallization layers, then power delivery is enhanced and electrical connections are improved, but device complexity increases
Solution Approach 1:
The patent designs TSVs to serve multiple functions: they provide mechanical support between dies, establish electrical connections for signals, and create vertical power delivery paths. This multi-functionality reduces the need for separate structures, offsetting the complexity of the extended TSV design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher interconnect density, reduced resistance, and increased yields by minimizing interference and enhancing power delivery in face-to-face semiconductor die arrangements, enabling the use of inductors for high-speed clock operation and power filtering.
Implementation Method 1
a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die
Data Source
AI summary
In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.