Face-to-Face IC Package Stacking for I/O Pad Density Limits
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Solution Overview
Problem
As semiconductor technologies advance, the increasing density of input/output (I/O) pads on integrated circuit dies complicates packaging due to reduced available area, necessitating innovative solutions for enhanced parallel processing capabilities.
Innovation Solution
The approach involves forming an integrated circuit package by stacking memory devices on a processor device without integrated memories, using hybrid bonding to connect them, which reduces interconnect length and improves performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuit dies are made smaller to increase density, then the number of functions integrated increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of I/O pads on the die surface to a three-dimensional stacked architecture where multiple dies are vertically arranged. This dimensional change allows I/O pads to be distributed across multiple layers and surfaces, effectively increasing the available I/O area without increasing the die footprint.
Solution Approach 2:
The patent divides a single large die into multiple smaller dies that are stacked vertically. Each die can have its own I/O pads, and the combined I/O capacity of all dies exceeds that of a single die of equivalent total area. This segmentation allows I/O pads to be distributed across multiple components rather than constrained to a single planar surface.
2Productivity
If the density of I/O pads is increased to accommodate more functions, then parallel processing capability improves, but packaging difficulty increases
Solution Approach 1:
The patent resolves packaging difficulty by moving from planar I/O pad arrangement to a vertical stacking configuration. This three-dimensional arrangement distributes I/O pads across multiple layers and facilitates heat dissipation, thereby improving parallel processing capability while simplifying the packaging process through standardized vertical interconnections.
3Quantity of substance
If multiple dies are stacked to increase parallel processing capability, then memory capacity and processing units increase, but interconnect length should be reduced
Solution Approach 1:
The patent implements vertical stacking of multiple dies with direct face-to-face bonding, creating short interconnect paths through the thickness of the stack. This three-dimensional configuration reduces interconnect length compared to lateral routing on a single large die, as signals travel vertically through minimal distances between adjacent die layers.
Data Source
AI summary
In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.