Face-to-Face Stacked IC Package with Molded Chip Substrate
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Solution Overview
Problem
Consumer electronics require more integrated circuits in a shrinking physical space with decreasing cost, while existing technologies fail to fully address the need for low profile, high yield, and cost reduction in stacked integrated circuit packages.
Innovation Solution
The solution involves forming molded chips with a face-to-face configuration, where conductors are attached to a wafer, encapsulated, and connected with electrical interconnects, allowing for efficient stacking and reduced substrate dimensions, using existing manufacturing processes and equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuits are stacked into a single package to increase functionality, then the number of integrated circuits in the package increases, but the package height and manufacturing complexity increase resulting in decreased yield and increased cost
Solution Approach 1:
The patent merges the spacer structure with the encapsulant material, creating a unified component that performs both spacing and encapsulation functions. This eliminates the need for separate spacer fabrication and insertion processes, thereby reducing manufacturing complexity while maintaining the ability to stack multiple integrated circuits vertically
Solution Approach 2:
The encapsulant is designed to serve multiple functions simultaneously: it provides mechanical support, electrical insulation, environmental protection, and spacing between chips. This multi-functionality reduces the number of separate components and processes needed, simplifying manufacturing while enabling higher circuit density
2Stability of the object's composition
If spacers are used between integrated circuits in a stack to maintain spacing, then the structural integrity is improved, but additional manufacturing processes are required increasing complexity and cost
Solution Approach 1:
The spacer functionality is merged into the encapsulant material itself. The encapsulant is applied in a manner that automatically creates the necessary spacing between chips during the encapsulation process, eliminating the need for separate spacer components and their associated fabrication and insertion processes
Solution Approach 2:
The encapsulation process itself performs the spacing function. By controlling the application of the encapsulant material, the system automatically establishes the required inter-chip spacing without requiring external spacer components, thereby simplifying manufacturing while maintaining structural integrity
3Area of stationary object
If the package dimensions are reduced to save space, then the physical footprint is decreased, but the manufacturing precision requirements increase
Solution Approach 1:
The patent changes the dimensional parameters of the encapsulant material and its application process to accommodate smaller package footprints. By adjusting the thickness and lateral dimensions of the encapsulant, the system achieves compact packaging while maintaining adequate spacing and alignment tolerances for manufacturing
Data Source
AI summary
A stacked integrated circuit package system is provided forming a first molded chip comprises attaching a conductor on a wafer, applying an encapsulant around the conductor, and exposing a surface of the conductor in the encapsulant, attaching a first electrical interconnect on the conductor of the first molded chip and stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.