Face-to-Face Stacked Memory with Per-Tile Timing Control
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Solution Overview
Problem
The design and construction of stacked semiconductor devices with multiple memory tiles controlled by a single logic chip are complicated due to varying signal path lengths and setup/hold time requirements, making it difficult to achieve uniform signal characteristics across all tiles.
Innovation Solution
Incorporation of timing adjustment devices, including selectors and flip-flops, in each memory tile to adjust setup and hold times for input and output signals relative to a clock signal, allowing for flexible design and uniform signal characteristics across memory tiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single logic chip controls multiple memory tiles, then the device integration is improved, but the signal path length variation and timing skew increase
Solution Approach 1:
The patent divides the memory chip into multiple independent memory tiles (MT0-MT7), each with its own timing adjustment device. This segmentation allows each tile to independently adjust its timing parameters, compensating for the signal path length variations that occur when controlled by a single logic chip, thereby maintaining timing uniformity across all tiles.
Solution Approach 2:
The patent introduces timing adjustment devices as intermediary components between the logic chip and memory tiles. These devices include setup/hold time adjustors and output delay/skew time adjustors that act as mediators to compensate for timing variations caused by different signal path lengths, ensuring uniform timing characteristics across all memory tiles.
2Manufacturing precision
If wire tree-structure signal lines are designed to achieve equal wiring length, then timing uniformity is improved, but the design complexity increases
Solution Approach 1:
The patent changes the approach from geometric parameter optimization (equal wiring length through wire tree structure) to temporal parameter adjustment (setup/hold time and output delay/skew time). By allowing different wiring lengths and compensating through timing parameter adjustments in each memory tile, the design complexity is significantly reduced while maintaining timing uniformity.
3Manufacturing precision
If multiple logic memory controllers are used to control memory tiles, then timing control precision is improved, but the logic chip size increases
Solution Approach 1:
The patent implements self-service timing adjustment by equipping each memory tile with its own timing adjustment device. Instead of requiring multiple logic memory controllers to provide centralized timing control, each tile independently adjusts its own setup/hold time and output delay/skew time, eliminating the need for additional logic controllers and reducing the logic chip area.
Data Source
AI summary
A stacked memory with a timing adjustment function is provided, including a logic chip; a memory chip coupled to the logic chip in a face-to-face manner and including plural memory tiles; plural timing adjustment devices, respectively provided in each memory tile, wherein for each memory tile, each timing adjustment device further includes a first timing adjustment device that is configured to adjust setup times and hold times for a command and an address with respect to an edge of a clock signal and a second timing adjustment device that is configured to adjust a setup time and a hold time for input data with respect to the edge of the clock signal.