Faceted Intrinsic Buffer for Transistor Stress and Short Channel Effects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Field effect transistors face challenges in minimizing short channel effects while maximizing stress effects in embedded source and drain regions, which degrades junction profiles and carrier mobility, necessitating a method to optimize dopant concentration and stress levels.
Innovation Solution
A faceted intrinsic buffer semiconductor material is deposited on the sidewalls of source and drain trenches by selective epitaxy, allowing greater dopant outdiffusion and suppressing diffusion in uniform regions, followed by in-situ doped selective epitaxy to fill the trenches with doped semiconductor material, creating a graded-doping semiconductor portion that minimizes short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high level dopant concentration is increased to provide low on-resistance, then on-resistance decreases, but short channel effects are degraded due to junction profile degradation
Solution Approach 1:
The source and drain regions are segmented into multiple zones with different doping concentrations: a lightly-doped extension region adjacent to the channel and a heavily-doped deep region below the extension region. This segmentation allows the extension region to maintain a sharp junction profile (minimizing short channel effects) while the deep region provides high dopant concentration (low on-resistance).
Solution Approach 2:
Different regions of the source/drain structure are assigned different doping qualities: the extension region has low dopant concentration with sharp junctions for optimal channel control, while the deep region has high dopant concentration for low resistance. This local quality differentiation resolves the contradiction between low on-resistance and junction profile quality.
2Reliability
If high level dopant activation is achieved by anneal at higher temperature, then dopant activation increases, but junction profile is degraded
Solution Approach 1:
The doping structure is segmented vertically into extension and deep regions, allowing the extension region to maintain sharp junctions after annealing while the deep region provides activated dopants for low resistance. The segmentation protects the junction profile from degradation during high-temperature activation processes.
Solution Approach 2:
The lightly-doped extension region acts as an intermediary between the channel and the heavily-doped deep region. It serves as a buffer that protects the channel junction from dopant diffusion during activation annealing, while still allowing sufficient dopant activation in the deep region to achieve low on-resistance.
3Reliability
If volume of epitaxial stressor materials is increased to improve carrier mobility, then stress level increases, but proximity between source and drain regions is reduced causing degraded short channel effects
Solution Approach 1:
The stressor materials are positioned in the vertical dimension (below the channel) rather than expanding laterally. This vertical placement provides stress to the channel for improved carrier mobility while maintaining adequate lateral spacing between source and drain regions, preventing short channel effect degradation.
Solution Approach 2:
Stress is applied locally to the channel region through vertically-positioned stressor materials, providing the necessary stress for carrier mobility improvement without affecting the lateral dimensions. This localized stress application avoids the trade-off between stress level and source-drain spacing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility and reduces short channel effects by optimizing dopant distribution and stress levels, leading to improved performance and reduced on-resistance in field effect transistors.
Implementation Method 1
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy
Implementation Method 2
Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width
Data Source
AI summary
A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.