Multi-fin FinFETs with Faceted Source-Drain Gaps
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Solution Overview
Problem
The instability of the gate dielectric layer and work function metal layer in finFETs poses challenges in the fabrication of multi-fin finFETs, particularly due to the complex 3D topography and the need for a replacement metal gate process that avoids damaging processing steps.
Innovation Solution
The method involves forming dummy semiconductor regions between fins, creating a sacrificial gate, growing faceted semiconductor regions that intersect with the gate to form gaps, depositing a dielectric layer to fill these gaps, and replacing the sacrificial gate with a replacement metal gate, thereby avoiding direct contact and simplifying the gate replacement process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sacrificial gate is formed over semiconductor fins prior to forming source/drain regions, then the gate dielectric layer and work function metal layer can be deposited without damage, but the complex 3D topography makes complete removal of the sacrificial gate difficult without forming spacers on the fins
Solution Approach 1:
The source/drain regions are segmented into faceted semiconductor regions that grow on specific crystallographic planes. These faceted regions create natural gaps between the source/drain and gate, allowing the sacrificial gate to be completely removed without leaving spacers. The segmentation of the source/drain into distinct faceted regions resolves the contradiction by providing a structural solution to the removal problem while maintaining gate stability.
Solution Approach 2:
The faceted semiconductor regions act as an intermediary structure between the source/drain and the gate. By growing these faceted regions with specific orientations, gaps are formed that facilitate complete sacrificial gate removal. This intermediary structure mediates between the need for gate stability during deposition and the need for complete gate removal afterward, eliminating the spacer formation problem.
2Ease of manufacture
If dummy semiconductor regions are grown on sidewalls of fins to merge fins, then multi-fin finFET structures can be formed, but the additional processing steps increase fabrication complexity
Solution Approach 1:
The dummy semiconductor regions grown on the sidewalls of adjacent fins merge together to form continuous source/drain regions. This merging process automatically creates the desired multi-fin finFET structure with proper electrical connections between fins. By combining the fin structures through the dummy regions, the fabrication process achieves the desired device architecture while the subsequent faceting and gap formation simplify the overall process by enabling complete sacrificial gate removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful formation of multi-fin finFET structures with replacement metal gates and faceted source/drain regions, overcoming the difficulties associated with the 3D topography and ensuring the complete removal of the sacrificial gate without forming spacers on the fins, thus enhancing the reliability and efficiency of the fabrication process.
Implementation Method 1
growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate
Data Source
AI summary
A semiconductor structure including semiconductor fins, a gate over a middle portion of the semiconductor fins, and faceted semiconductor regions outside of the gate separated from gaps may be formed. The semiconductor structure may be formed by forming fins on a semiconductor substrate where each fin has a pair of sidewalls aligned parallel to the length of the fin, growing dummy semiconductor regions on the sidewalls of the fins, forming a sacrificial gate that covers a center portion of the fins and the dummy semiconductor regions, removing portions of the dummy semiconductor regions not covered by the sacrificial gate, and growing faceted semiconductor regions on the sidewalls of the portions of the fins not covered by the sacrificial gate. The faceted semiconductor regions may intersect to form gaps between the faceted semiconductor regions and the gate.