Faceted Raised Source/Drain Epi Material for Transistor Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistor devices shrink, the volume of epitaxial semiconductor material in source/drain regions decreases, leading to increased resistance and reduced effectiveness in imparting desired stress conditions on the channel region, limiting the performance of modern transistors.
Innovation Solution
The method involves forming enhanced faceted raised source/drain epi material by creating a first straight sidewall spacer, a recessed layer of sacrificial material, and a second straight sidewall spacer, followed by epitaxial growth, where the epi semiconductor material engages the outer surface of the first sidewall spacer and the bottom surface of the second sidewall spacer, increasing the volume and effectiveness of the epi material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase integration density, then chip area utilization improves, but the volume of epi semiconductor material in source/drain regions decreases leading to increased resistance
Solution Approach 1:
The patent implements a multi-layer spacer structure where a first sidewall spacer is formed on the gate, a sacrificial layer is deposited and recessed, and a second sidewall spacer is formed on the first spacer. This nested arrangement creates an expanded mold cavity that allows formation of larger volume epi material in scaled devices, resolving the contradiction between high integration density and adequate source/drain resistance.
Solution Approach 2:
The patent transitions from traditional single-layer spacers to a three-dimensional multi-layer spacer structure with vertical stacking. By adding the sacrificial layer between two spacer layers, the mold cavity extends in the vertical dimension, enabling increased epi material volume without increasing lateral footprint, thus maintaining integration density while improving electrical performance.
2Productivity
If device dimensions are shrunk to increase integration density, then chip area utilization improves, but the effectiveness of epi material in imparting stress conditions on the channel region is reduced
Solution Approach 1:
The nested multi-layer spacer structure creates an expanded cavity that accommodates increased volume of epi semiconductor material. This larger volume of epi material provides sufficient stress to the channel region even in scaled devices, maintaining stress effectiveness while achieving high integration density through vertical structure optimization.
Solution Approach 2:
The patent changes the geometric parameters of the spacer structure by introducing multiple layers with different thicknesses and positioning. This parameter optimization allows the mold cavity to generate adequate epi material volume for stress application without increasing the device footprint, thus maintaining both integration density and stress effectiveness.
3Reliability
If the volume of epi semiconductor material is increased to reduce resistance and improve stress, then device performance improves, but the device complexity and fabrication process steps increase
Solution Approach 1:
The sacrificial layer is deposited and recessed in advance before final epi material formation. This preliminary action creates the expanded mold cavity structure beforehand, allowing subsequent epi growth to naturally fill the larger volume. The complex multi-layer structure is built incrementally through pre-planned fabrication steps, making the process manageable despite increased complexity.
Solution Approach 2:
The sacrificial layer serves as an intermediary element that enables cavity expansion without requiring direct complex patterning of the final epi structure. By using this temporary intermediate structure, the fabrication process achieves the complex multi-layer spacer geometry through sequential deposition and etching steps rather than requiring sophisticated lithography for the final structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a significantly larger volume of epi semiconductor material, reducing contact resistance and enhancing device performance by improving stress conditions in the channel region, potentially increasing operating speed and electrical performance of transistors.
Implementation Method 1
forming an epi semiconductor material on and above the substrate, wherein an edge of the epi semiconductor material engages the first vertical portion of the outer surface of the first straight sidewall spacer
Data Source
AI summary
One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.