Faceted Raised Source/Drain Epi for Transistor Resistance
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Solution Overview
Problem
As transistor devices shrink, the volume of epitaxial semiconductor material in source/drain regions decreases, leading to increased resistance and reduced effectiveness in imparting desired stress conditions on the channel region, limiting performance enhancement.
Innovation Solution
The method involves forming enhanced faceted raised source/drain epi material by creating a first straight sidewall spacer, a second straight sidewall spacer, and a recessed sacrificial layer, allowing for increased volume of epi semiconductor material engagement, which enhances stress conditions and reduces resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are shrunk to increase integration density, then chip area utilization improves, but the volume of epi semiconductor material in source/drain regions decreases leading to increased resistance and reduced stress effectiveness
Solution Approach 1:
The patent implements a multi-layer spacer structure where a first spacer is formed on the gate, a second spacer is formed on the first spacer, and a third spacer is formed on the second spacer. This nested arrangement creates progressively larger source/drain regions while maintaining compact device footprint, effectively nesting multiple structural levels to achieve volume expansion without increasing planar area.
Solution Approach 2:
The patent transitions from two-dimensional planar source/drain regions to three-dimensional raised regions by forming spacers at multiple vertical levels. The source/drain regions are constructed with height variations, creating a stepped or faceted three-dimensional structure that increases material volume while maintaining compatibility with scaled device dimensions.
2Productivity
If device dimensions are shrunk to increase integration density, then chip area utilization improves, but the effectiveness of epi semiconductor material in imparting stress conditions on the channel region is reduced
Solution Approach 1:
The multi-layer spacer structure creates expanded source/drain regions that provide sufficient volume to generate and transmit effective stress conditions to the channel. By nesting spacers at multiple levels, the structure maintains mechanical coupling with the channel while providing adequate material volume for stress generation, resolving the conflict between device scaling and stress effectiveness.
Solution Approach 2:
The patent employs different semiconductor materials with distinct stress properties in the source and drain regions. The epi semiconductor material is specifically selected and structured to provide desired stress conditions (tensile or compressive) to the channel, creating a composite structure where material composition is optimized for stress transmission while maintaining electrical functionality.
3Reliability
If the volume of epi semiconductor material is increased to reduce resistance and improve stress effectiveness, then device performance improves, but device dimensions and integration density are reduced
Solution Approach 1:
The patent increases source/drain material volume by extending structures vertically through multi-layer spacer formation rather than expanding laterally. The raised source/drain regions utilize the third dimension (height) to provide increased material volume for reduced resistance and stress effectiveness while maintaining compact planar dimensions suitable for high integration density.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the source and drain regions are formed with increased volume and height through spacer structures, while the channel region maintains its scaled dimensions. This local differentiation allows volume expansion where needed for electrical performance without compromising overall device scaling and integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the volume of epi semiconductor material, reducing contact resistance and improving device performance by effectively imparting desired stress conditions on the channel region.
Implementation Method 1
forming an epi semiconductor material such that an edge of the epi semiconductor material engages the outer surface of the first vertical portion of the second straight sidewall spacer
Data Source
AI summary
One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a second straight sidewall spacer on the first straight sidewall spacer and forming a recessed layer of sacrificial material adjacent the second straight sidewall spacer such that the recessed layer of sacrificial material covers an outer surface of a first vertical portion of the second straight sidewall spacer while exposing a second vertical portion of the second straight sidewall spacer. In this example, the method may also include removing the second vertical portion of the second straight sidewall spacer, removing the recessed layer of sacrificial material and forming an epi material such that an edge of the epi material engages the outer surface of the first vertical portion of the second straight sidewall spacer.