Faceted Source Drain Transistor Reducing Parasitic Capacitance
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Solution Overview
Problem
Conventional field effect transistors face limitations due to high parasitic capacitances and channel silicidation issues, particularly with faceted source and drain regions, which affect electrical performance and reliability.
Innovation Solution
A field effect transistor design featuring faceted source and drain regions with a bilayer structure, where the upper main face of the first layer is completely covered by the second layer, reducing channel access resistances and preventing channel silicidation, while using epitaxy processes to produce the faceted crystal structure with specific dopant concentrations and layer thicknesses to enhance contact and reduce parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the thickness of source/drain regions is reduced to reduce parasitic capacitance, then parasitic capacitance decreases, but the number of dopants that can diffuse into the channel decreases and silicidation risk increases
Solution Approach 1:
The source/drain region is segmented into multiple layers with different orientations. The first layer has a first orientation and the second layer has a second orientation different from the first, allowing each layer to contribute differently to capacitance reduction and dopant diffusion while maintaining structural integrity and controlling silicidation.
Solution Approach 2:
Different regions of the source/drain structure are given different properties through the layered approach. The first layer and second layer have different orientations, creating local variations in how dopants diffuse and how capacitance is formed, allowing optimization of both capacitance reduction and dopant diffusion in different parts of the structure.
2Object-generated harmful factors
If faceted source/drain regions are produced to reduce parasitic capacitance, then parasitic capacitance decreases, but channel silicidation risk increases and spacer thickness fluctuations occur
Solution Approach 1:
The faceted structure is segmented into multiple layers with different orientations. This segmentation allows the faceted geometry to reduce capacitance while the layered structure prevents direct exposure of the channel to silicidation-prone surfaces and reduces spacer thickness fluctuations by distributing the structural variations across layers.
Solution Approach 2:
The source/drain region uses a composite structure with at least two layers of crystalline semiconductor material having different orientations. This composite approach combines the capacitance-reducing benefits of faceting with the protective effects of multiple layers, preventing channel silicidation and reducing spacer thickness variations.
3Object-affected harmful factors
If the upper main face of the first layer is partially covered with insulating spacer, then channel protection is improved, but channel access resistance increases
Solution Approach 1:
The source/drain region is segmented into multiple layers, with the second layer completely covering the upper main face of the first layer. This segmentation allows the second layer to provide channel protection while the first layer maintains electrical contact, reducing channel access resistance compared to partial spacer coverage.
Solution Approach 2:
The second layer is merged with the first layer to form an integrated structure where the upper main face of the first layer is completely covered by the second layer. This merging provides both channel protection and maintains electrical continuity, reducing access resistance while protecting the channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces parasitic capacitances, protects the channel from metallization, and ensures efficient contact formation, leading to improved electrical performance and reliability by minimizing channel access resistances and silicidation risks.
Implementation Method 1
The electrical properties of MOS transistors are limited by various capacitances: contact capacitance between gate 101 and the contacts deposited on the metallizations of source/drain regions 104a, 104b, capacitance between gate 101 and source/drain regions 104a, 104b via the spacers 103 (called 'capacitance out of fringe'), direct overlap capacitance between the gate 101 and the extensions 105a, 105b of the source/drain regions 104a, 104b ('capacitance of direct overlap').
Implementation Method 2
The faceted crystal structure forming the source region and/or the drain region is free of defects. The transistor is more efficient.
Data Source
Figure 1a~2
Figure 3~5
AI summary
Field-effect transistor whose source (230a) and drain (230b) regions are formed of a crystalline structure comprising: - a first layer (231a, 231b) comprising two parallel principal faces and two parallel lateral faces, the principal faces being perpendicular to the lateral faces, - a second layer (232a, 232b) covering the first layer (231a, 231b), the second layer (232a, 232b) comprising a first principal face and a second principal face parallel to each other and two lateral faces, the first principal face being in contact with the first layer (231a, 231b), the lateral faces forming an angle alpha ranging from 50° to 59°, and preferably 53°, with the first principal face.