Facilitator Die Hierarchies for High-Layer 3D IC Stacks
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Solution Overview
Problem
Current 3D IC designs are limited in total stack size due to fly-by wire requirements, latency, and voltage drop considerations, as each die is serviced from a single wire connected back to the bottom die, restricting the number of layers and increasing connectivity burden with each added circuit layer.
Innovation Solution
Incorporating facilitator dies within a heterogeneous die stack, which serve as a hierarchical contact layer for signal connections and power distribution between the bottom die and upper dies, allowing for arbitrary stack heights and flexible placement of facilitator dies throughout the stack, decoupling from fly-by wire requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fly-by wire configuration is used with single bottom die servicing all upper dies, then connectivity is simplified, but total stack size is limited due to voltage drop and latency
Solution Approach 1:
The patent segments the hierarchical servicing structure by introducing intermediate facilitator dies that divide the stack into multiple tiers. Each facilitator die services a subset of upper dies, creating a tree-like hierarchy rather than a single bottom-die-to-all configuration. This segmentation reduces the connectivity burden on any single die while enabling greater stack heights.
Solution Approach 2:
The patent transitions from a one-dimensional fly-by configuration (single wire from bottom die to all upper dies) to a multi-dimensional hierarchical structure where facilitator dies are distributed throughout the stack at different vertical positions. This dimensional change allows arbitrary stack heights by decoupling the servicing relationship from strict bottom-die-centric topology.
2Productivity
If more circuit layers are added to increase stack size, then device functionality is improved, but connectivity burden on bottom die increases
Solution Approach 1:
The patent segments the connectivity burden by distributing facilitator dies throughout the stack. Each facilitator die assumes responsibility for servicing a specific subset of upper dies, thereby segmenting the total connectivity burden across multiple intermediate nodes rather than concentrating it all at the bottom die.
Solution Approach 2:
The facilitator dies act as intermediary nodes between the bottom die and the upper dies. These intermediaries receive signals from the bottom die and distribute them to their respective subsets of upper dies, thereby reducing the direct connectivity burden on the bottom die while enabling more circuit layers to be stacked.
3Adaptability or versatility
If heterogeneous die types are used to optimize components, then component performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs facilitator dies that serve multiple functions: they act as intermediate servicing nodes for upper dies, provide power distribution, and can be of heterogeneous types to match the specific requirements of different upper die subsets. This multi-functionality allows component optimization while managing manufacturing complexity through standardized facilitator die designs.
Data Source
AI summary
Embodiments of the present invention are directed to processing methods and resulting structures for three-dimensional integrated circuits (3D ICs) having facilitator dies in a hierarchical configuration. In a non-limiting embodiment, a method includes forming a plurality of stacked dies. The plurality of stacked dies includes a bottom die having a first die type, a plurality of upper dies having a second die type different than the first die type, and a facilitator die having a third die type different than the first die type and the second die type. At least one of a signal connection and a power distribution line are formed hierarchically between the bottom die, the plurality of upper dies, and the facilitator die.