DRAM Cell Array Facing Bar Layout Area Reduction
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Solution Overview
Problem
Current dynamic random access memory (DRAM) cell arrays face challenges in reducing layout area effectively, particularly with cell transistors having vertical pillars, which limit further reduction in layout area.
Innovation Solution
A DRAM cell array design where each DRAM cell pair consists of a first and second DRAM cell, with a facing bar dividing active areas into sub-regions, shared bit line plugs, and word lines on the side surfaces of the facing bar, allowing for reduced layout area through efficient transistor and storage configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If cell transistors with vertical pillars are used, then transmission channel length is maintained, but layout area reduction is limited
Solution Approach 1:
The patent transitions from conventional planar transistor structures to vertical FinFET structures, utilizing the third dimension (vertical height) to achieve the required transmission channel length. The FinFETs extend vertically from the semiconductor substrate, allowing sufficient channel length without occupying excessive lateral layout area, thus resolving the contradiction between maintaining channel length and reducing layout area.
2Reliability
If one pillar per DRAM cell is implemented, then transmission channel is formed, but layout area cannot be reduced further
Solution Approach 1:
The patent merges multiple DRAM cells into shared cell pairs, where adjacent cell pairs share common bit line plugs and word line structures. This merging approach reduces the overall layout area by eliminating redundant structures while maintaining the necessary transmission channels through the vertical FinFET architecture, allowing reliable channel formation with reduced area per cell.
Solution Approach 2:
The shared bit line plugs and word line structures serve multiple DRAM cells simultaneously, providing multi-functionality. The vertical FinFETs in adjacent cell pairs share common control lines and bit line connections, allowing these structures to perform the same function for multiple cells, thereby reducing the total layout area required while maintaining reliable transmission channels for all cells.
3Area of stationary object
If facing bar structure with shared bit line plugs is used, then layout area is reduced, but device complexity increases
Solution Approach 1:
The patent segments the DRAM cell array into repeating cell pair units, each with a standardized configuration of vertical FinFETs, shared bit line plugs, and word line structures. This segmentation into modular units simplifies the overall design by creating a repetitive pattern that, while complex in individual detail, provides regularity and predictability across the entire array, making the complexity manageable through standardization.
Data Source
AI summary
A dynamic random access memory (DRAM) cell array using facing bars and a method of fabricating the DRAM cell array are disclosed. A first DRAM cell and a second DRAM cell of each of DRAM cell pairs of a DRAM cell array fabricated using a method of fabricating a DRAM cell array share a facing bar and a bit line plug therebetween. Thus, the overall layout area is greatly reduced by a DRAM cell array fabricated using the method of fabricating the DRAM cell array. Further, in the method of fabricating the DRAM cell array, a storage of each of the DRAM cells of the DRAM cell array is formed as a multi-fin type having a plurality of lateral protrusions, thereby greatly increasing an area of the storage.