Factorized Power Accelerator for Fast CPU/GPU Load Transients
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Solution Overview
Problem
Current power systems struggle to efficiently supply high currents to semiconductor loads like CPUs and GPUs due to limitations in transient performance, power distribution network losses, and impedance, which can lead to voltage drops and peak transient voltage levels exceeding acceptable limits.
Innovation Solution
The implementation of a factorized power supply apparatus that includes a switching regulator, a current multiplier stage with switching power conversion circuitry, and an accelerator circuit. The accelerator circuit detects perturbances in the output voltage and supplies transient power to the factorized bus, with a response time shorter than the regulator's response time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a linear regulator is used to provide logic level voltages to VLSI, then fast transient responses can be achieved, but it cannot keep up with high current draw and steplike changes in current
Solution Approach 1:
The power supply system is divided into two independent stages: a switching regulator stage for bulk power conversion and a linear regulator stage for fine voltage control. This segmentation allows each stage to operate within its optimal performance range, with the switching regulator handling high current demands and the linear regulator providing fast transient response for voltage regulation.
Solution Approach 2:
A factorized bus serving as an intermediary power distribution network is introduced between the switching regulator and the load. This factorized bus architecture with controlled impedance provides a low-inductance path for high current while maintaining voltage stability, enabling both high power delivery and fast transient response.
2Power
If high current levels are supplied to VLSI devices, then power requirements are met, but power distribution network losses and impedance have significant impacts
Solution Approach 1:
The power distribution network is designed with locally optimized characteristics, including controlled impedance traces and strategic placement of decoupling capacitors near high-current draws. The factorized bus implements varying impedance characteristics at different frequencies to minimize losses at specific operating points while maintaining high current capability.
Solution Approach 2:
The system dynamically adjusts operating parameters including switching frequency, duty cycle, and impedance matching to optimize the balance between current delivery and loss minimization. The switching regulator operates at optimized frequencies to reduce resistive and reactive losses in the PDN while maintaining required current levels.
3Loss of energy
If a switching regulator is used for high current conversion, then power efficiency is improved, but transient response is slower compared to linear regulators
Solution Approach 1:
The switching regulator pre-charges and pre-positiones energy in the factorized bus and output capacitors in anticipation of expected load transients. The control system uses predictive algorithms to prepare the power delivery network before transient events occur, enabling faster response without sacrificing efficiency.
Solution Approach 2:
The switching regulator employs periodic switching at optimized frequencies to deliver power in controlled pulses that maintain efficiency while the factorized bus and output capacitance smooth these pulses to provide continuous stable voltage. This periodic energy transfer enables efficient power conversion with improved transient characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution significantly improves the transient response of the power system, allowing it to meet the rapid transient demands of high-current semiconductor devices, thereby reducing voltage drops and peak transient voltage levels, and enhancing overall power delivery efficiency.
Implementation Method 1
providing a switching regulator having a regulator input connected to receive power from a source and a regulator output for delivering a controlled voltage
Implementation Method 2
the accelerator having an error input connected to detect perturbances in the output voltage, Vout
Data Source
AI summary
The system response time of a factorized power architecture may be reduced using a high bandwidth accelerator connected in parallel with a low bandwidth switching regulator to feed one or more downstream high bandwidth current multipliers, e.g. at the point of load. The accelerator may use a high speed linear amplifier to drive the factorized bus using stored energy derived from the bus or a low voltage bias supply. The accelerator may alternatively be connected in series between the switching regulator and the downstream current multipliers.