Factory Reset Circuit Using Flip-Flop Signal Latching
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Solution Overview
Problem
The high production and research and development costs associated with implementing a factory reset function in communications devices due to the need for complex and costly hardware circuits, such as CPLDs, to detect and process reset signals.
Innovation Solution
A factory reset apparatus and method utilizing a reset switch, a flip-flop, and a processor, where the reset switch generates a low-level reset signal that triggers the flip-flop to latch and output a reset request signal, allowing the processor to perform a factory reset operation, thereby simplifying the circuit and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a CPLD or similar hardware circuit is used to detect and process reset signals for factory reset function, then the factory reset function can be implemented, but the hardware circuit complexity and production costs increase
Solution Approach 1:
The patent extracts the timing and detection functions from the CPLD hardware circuit and relocates them to software implementation within the processor. This removes the need for complex dedicated hardware timing circuits while preserving the factory reset functionality. The reset button press duration is now detected and measured by software rather than hardware logic.
Solution Approach 2:
The patent replaces the mechanical/electronic hardware timing circuit (CPLD) with a software-based timing mechanism. The processor uses its internal clock and software timers to measure the duration of the reset button press, substituting physical hardware timing components with software logic that achieves the same functional result with lower hardware complexity.
2Reliability
If a CPLD or similar hardware circuit is used to detect and process reset signals for factory reset function, then the factory reset function can be implemented, but the production and research and development costs increase
Solution Approach 1:
The patent extracts the timing and detection functions from the CPLD hardware circuit and relocates them to software implementation within the processor. This removes the need for complex dedicated hardware timing circuits while preserving the factory reset functionality. The reset button press duration is now detected and measured by software rather than hardware logic.
Solution Approach 2:
The patent uses the processor's existing software environment and internal resources (clock, timers) to perform timing functions that would otherwise require expensive dedicated hardware. This approach uses readily available, low-cost software capabilities instead of investing in costly hardware components, thereby reducing production and development costs.
Data Source
AI summary
A factory reset apparatus includes a reset switch, a first power supply module, a flip-flop, and a CPU. The flip-flop includes a data input pin, a clock pin, and a true flip-flop output pin. The reset switch is connected to the data input pin, the first power supply module is connected to the clock pin, and the true flip-flop output pin is connected to the CPU. The reset switch generates a low-level reset signal when being pressed; the flip-flop receives an electrical signal from the clock pin. A rising edge of the electrical signal triggers the flip-flop to latch a low-level state of the reset signal. The flip-flop outputs a low-level reset request signal from the true flip-flop output pin according to the latched low-level state of the reset signal. The CPU starts a factory reset operation according to the reset request signal.