Fail Bit Counting Circuit Using Segmented Page Buffers
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Solution Overview
Problem
Conventional fail bit counting circuits in NAND type flash memory devices suffer from low accuracy and slow operation due to analog circuitry and noise sensitivity, leading to increased operation time and insufficient detection accuracy.
Innovation Solution
A fail bit number counting circuit that divides the page buffer into segments and uses a series circuit with switch elements to differentiate between pass and fail bits, employing a clock counter to count the number of clocks required to transfer the counting enable signal, thereby improving accuracy and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog circuitry is used for fail bit counting, then the circuit can be implemented with simpler components, but the detection accuracy becomes insufficient and operation time increases
Solution Approach 1:
The patent replaces the conventional analog circuitry with a digital circuit implementation. The fail bit counting is performed using digital logic circuits including AND gates, OR gates, and flip-flops that process digital signals from the page buffer. This substitution of analog with digital systems resolves the contradiction by providing both high detection accuracy through precise digital signal processing and reduced operation time through parallel processing capabilities of digital circuits.
2Productivity
If the page buffer is processed as a whole, then the counting process is simpler to implement, but the operation time increases due to sequential processing
Solution Approach 1:
The patent divides the page buffer into multiple segments, with each segment processed by a separate counting circuit. The page buffer is partitioned into several groups of bits, and each group is fed to a dedicated AND gate and OR gate combination. This segmentation enables parallel processing of multiple bit groups simultaneously, significantly improving counting speed while the modular structure keeps individual circuit units relatively simple.
Solution Approach 2:
The patent merges multiple counting operations into a unified digital logic structure where AND gates, OR gates, and flip-flops work together in an integrated manner. The segmented counting results are combined through the OR gate to produce the final fail bit count, allowing parallel processing of multiple segments while maintaining a cohesive counting system that achieves high productivity without excessive complexity.
Data Source
AI summary
A fail bit number counting circuit includes a data transfer circuit configured by a series circuit in which switch elements turned on for calculation result data indicating a pass bit from each page buffer portion and turned off for calculation result data indicating a fail bit are connected in series; a control circuit inputs a counting enable signal to one input terminal of the data transfer circuit, and sequentially transfers the counting enable signal till the next switch element being turned off via the series circuit corresponding to a clock with a prescribed cycle; and the fail bit number counting circuit includes a clock counter by which the number of clocks till the counting enable signal reaches the other output terminal of the data transfer circuit after the counting enable signal is input to one input terminal of the data transfer circuit is counted as a fail bit number.