Fail Bit Repair Optimization in Integrated Circuit Chips
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Solution Overview
Problem
Current redundant circuit allocation methods for Fail Bit (FB) repair in integrated circuits are non-optimal, leading to incomplete repair of chips and reduced yield, as they fail to find an optimal repair combination due to excessive operational combinations exceeding the supported count.
Innovation Solution
The method involves determining target repair banks, performing compression processing, and allocating Redundant Bit-Lines (RBLs) and Word Lines (WLs) based on specific conditions to reduce the number of bits and improve processing efficiency, using a flowchart and state diagrams to guide the repair process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant circuit allocation method is used for FB repair, then chip repair capability is provided, but the method is non-optimal and cannot find the best repair combination
Solution Approach 1:
The patent segments the FB repair problem into multiple stages: initial repair processing for obvious cases, candidate combination generation, and optimal solution selection. This segmentation allows the system to handle complex repair scenarios by breaking them down into manageable steps, improving both reliability and manufacturability.
Solution Approach 2:
The patent performs preliminary action by pre-identifying and repairing obvious FB cases before generating candidate combinations. This preliminary repair processing reduces the complexity of subsequent optimization steps and ensures that easily repairable cases are handled first, improving overall repair efficiency.
2Reliability
If all possible repair combinations are evaluated to find optimal solution, then best repair combination can be found, but processing time and computational complexity increase
Solution Approach 1:
The patent applies partial action by evaluating only the necessary candidate combinations rather than all possible combinations. It generates candidate combinations based on specific criteria and selects from these candidates, avoiding the need to evaluate every possible repair scenario, thus reducing processing time while still finding optimal solutions.
Solution Approach 2:
The patent replaces exhaustive mechanical evaluation with an intelligent selection process. Instead of systematically checking all possible repair combinations, the system uses candidate combination generation and evaluation based on specific criteria, substituting brute-force computation with a more efficient algorithmic approach.
3Productivity
If redundant circuits are allocated to repair FBs, then chip yield can be improved, but determining optimal allocation is computationally intensive
Solution Approach 1:
The patent enables self-service by allowing the repair system to automatically identify candidate combinations and select optimal allocations without requiring complex external optimization tools. The system serves itself by generating and evaluating candidates based on built-in criteria, reducing the complexity of allocation determination while maintaining high chip yield.
Solution Approach 2:
The patent changes parameters by transforming the complex allocation problem into a candidate combination selection problem. It modifies the approach from evaluating all possible allocations to generating and selecting from specific candidate combinations based on defined parameters, thereby reducing computational complexity while improving productivity.
Data Source
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AI summary
The present disclosure involves a Fail Bit (FB) repair method and device, which relate to the technical field of integrated circuits and can be applied to a scene of repairing an FB in a chip. The method includes: a bank to be repaired of a chip to be repaired is determined; first repair processing is performed on a first FB using a redundant circuit; a bit position of a second FB in each target repair bank is determined, and second repair processing is performed on the second FB; an unrepaired FB in each target repair bank is determined, and candidate repair combinations of the unrepaired FBs and a candidate combination count are determined; and if the candidate combination count is greater than a combination count threshold, a target repair position is determined, and repair processing is performed on the target repair position using a Redundant Word-Line (RWL), the target repair position being a position of an FB that maximally reduces the candidate combination count after repair processing. The problem that no optimal repair combination for the FBs can be found and thus it is determined that the chip to be repaired may not be repaired successfully can be solved.