Fail Bit Repair Scheme Optimization for Integrated Circuits
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Solution Overview
Problem
Existing redundant circuit assignment methods for integrated circuit chips are non-optimal, leading to incomplete repair of Fail Bits (FBs) and reduced chip yield due to limited repair ranges and inefficient assignment of Redundant Word Lines (RWLs) and Redundant Bit Lines (RBLs.
Innovation Solution
A method and device for determining an optimal FB repair scheme by dividing the chip into target repair areas, performing initial repair processing using RWLs and RBLs, and determining candidate repair sub-schemes based on remaining RWLs and RBLs to minimize integrated repair cost, with the goal of achieving complete FB repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing non-optimal redundant circuit assignment methods are used, then the repair process is simpler, but the chip yield decreases due to incomplete FB repair
Solution Approach 1:
The patent divides the chip into multiple banks and further segments each bank into multiple repair regions. This segmentation allows the repair process to be broken down into manageable sub-problems, where each region can be independently analyzed and repaired using appropriate redundant circuits, thereby improving overall repair effectiveness and chip yield without overwhelming complexity
Solution Approach 2:
The patent employs a dynamic repair scheme selection mechanism that adapts to different repair scenarios. Based on the distribution and characteristics of fail bits in each region, the system dynamically selects the most appropriate repair scheme from multiple candidates, optimizing the use of limited redundant circuits and maximizing chip yield while maintaining manageable complexity through adaptive decision-making
2Device complexity
If limited redundant circuits are used, then the device complexity is reduced, but the repair completeness deteriorates
Solution Approach 1:
The patent applies local quality by tailoring repair strategies to specific regions based on their unique characteristics. Different repair schemes are assigned to different repair regions depending on the density and distribution of fail bits in each area. This allows limited redundant circuits to be optimally allocated where they are most needed, ensuring complete repair coverage without requiring excessive redundant resources across the entire chip
Solution Approach 2:
The patent changes the parameter of repair scheme selection based on the actual fail bit distribution and remaining redundant circuit availability. By dynamically adjusting which repair schemes are applied to which regions, the system maximizes repair completeness with limited redundant circuits, transforming a static resource allocation problem into a dynamic optimization process
3Reliability
If optimal repair schemes are implemented, then the repair effectiveness is improved, but the processing time increases
Solution Approach 1:
The patent reduces processing time by segmenting the chip into independent repair regions that can be processed in parallel. Each region's repair scheme can be determined and applied independently, allowing simultaneous processing across multiple regions rather than sequential analysis of the entire chip, thereby maintaining optimal repair effectiveness while significantly reducing total processing time
Solution Approach 2:
The patent performs preliminary analysis and classification of fail bit patterns to pre-determine suitable repair schemes for different region types. By categorizing repair regions based on their characteristics beforehand and pre-selecting appropriate repair strategies, the system avoids time-consuming real-time analysis during the actual repair process, thus improving repair effectiveness while minimizing processing time
Data Source
AI summary
A method for determining a Fail Bit (FB) repair scheme includes: a bank to be repaired of a chip to be repaired is determined, the bank to be repaired including multiple target repair areas; initial repair processing is performed on an FB in each of the target repair areas using a redundant circuit; responsive to that a number of remaining Redundant Word Lines (RWLs) is greater than 0 and a number of remaining Redundant Bit Lines (RBLs) is greater than 0, a candidate repair sub-scheme for each target repair area is determined, and a candidate repair cost corresponding to each candidate repair sub-scheme is determined; and a target repair scheme for the bank to be repaired is determined according to respective candidate repair sub-schemes and candidate repair costs, where the target repair scheme corresponds to a minimum integrated repair cost.