Fail Compare Procedure for Memory Data Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face challenges in efficiently verifying data read from memory devices, particularly due to increased latency and complexity when using XOR gates to determine comparator failures, which hinders the characterization and adjustment of reference voltages and sample times for comparators.
Innovation Solution
Implementing lookup tables to verify data read from memory devices, allowing for concurrent characterization of multiple comparators by disregarding specific bit failures and using a single set of expected bit information, thereby reducing latency and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If XOR gates are used to determine comparator failures by comparing read data to expected data, then data verification can be performed, but latency increases and complexity increases
Solution Approach 1:
The patent segments the data verification process by using separate lookup tables for different comparators. Each lookup table stores expected data for specific comparators, allowing parallel verification of multiple comparators simultaneously. This segmentation enables the system to avoid sequential testing while maintaining accurate failure detection for each comparator.
Solution Approach 2:
The patent implements preliminary action by pre-populating lookup tables with expected data for multiple comparators before the actual testing process. This allows the system to perform concurrent comparisons without calculating expected values during testing, thereby reducing latency while maintaining verification accuracy.
2Measurement precision
If one comparator is tested at a time to determine which comparator failed, then comparator performance can be characterized, but latency increases and complexity increases
Solution Approach 1:
The patent segments the comparator testing process by creating dedicated lookup tables for each comparator. Each lookup table contains expected data specific to that comparator, allowing the system to characterize each comparator's performance independently while processing multiple comparators in parallel. This maintains measurement precision while reducing overall testing complexity.
Solution Approach 2:
The patent implements a universal testing framework using a single controller and counter that can handle multiple comparators simultaneously. The lookup tables serve multiple purposes: storing expected data, enabling parallel comparisons, and facilitating performance characterization for all comparators through a unified process, thereby reducing complexity.
3Measurement precision
If different sets of expected data are generated to test each comparator, then accurate comparator characterization is possible, but complexity increases
Solution Approach 1:
The patent segments expected data into separate lookup tables for each comparator. Each lookup table stores pre-calculated expected data specific to that comparator's characteristics. This segmentation allows accurate comparator characterization while simplifying the testing process, as the controller only needs to select the appropriate lookup table rather than generating different data sets dynamically.
Data Source
AI summary
Methods, systems, and devices for a fail compare procedure are described. An apparatus may include a host device coupled with a memory device. An application specific integrated circuit (ASIC) associated with the host device (e.g., included in, coupled with) may include a set of comparators that output first bit information that includes respective states of at least two bits of data read from the memory device. The host device may compare (e.g., at the ASIC) the first bit information to second bit information that includes respective expected states of the at least two bits. Based on the comparison, the host device may determine whether a state of at least one bit of the first bit information is different than a state of a corresponding bit of the second bit information, and may output one or more signals including indications of a fail to a counter of the ASIC.