Fail Information Control Circuit for Semiconductor Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor technologies do not efficiently utilize memory space for error correction and repair operations, as they fail to effectively classify and count fail bits associated with memory errors.
Innovation Solution
A fail information control circuit that compares read and write data to generate discrimination signals for fail bits, counts these signals, and outputs corrected counts to efficiently manage memory usage by distinguishing between different types of failures, allowing for accurate ECC correction and repair operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fail bits are counted without classification, then the counting process is simple, but memory space utilization is inefficient
Solution Approach 1:
The patent segments fail bits into two distinct categories: first fail bits (where write data is '0' and read data is '1') and second fail bits (where write data is '1' and read data is '0'). This segmentation is achieved through separate discrimination circuits that generate different discrimination signals for each fail type, enabling independent counting and optimization of memory space utilization for each category.
2Productivity
If fail bits are classified and counted separately, then memory space utilization is improved, but the circuit complexity increases
Solution Approach 1:
The circuit is segmented into specialized sub-circuits: a comparison circuit for data comparison, a fail bit discrimination circuit that separates first and second fail discrimination signals, and a counter circuit with first and second counting units. Each segment handles a specific function, which while increasing component count, optimizes overall system efficiency through targeted processing of different fail types.
Solution Approach 2:
The counter circuit is designed with universal functionality to handle both first and second fail bits through its dual counting units. The same counter structure can process either fail type independently, providing a scalable solution that maintains consistency while handling multiple fail categories without requiring entirely separate counting mechanisms.
3Reliability
If all fail bits are treated uniformly, then error correction can be performed, but repair operations cannot efficiently distinguish between different fail types
Solution Approach 1:
The patent segments fail bit information into distinct categories that preserve both error correction capability and repair flexibility. First fail discrimination signals and second fail discrimination signals are generated separately, allowing ECC operations to process all fails while enabling repair operations to selectively address specific fail types based on their characteristics and locations.
Solution Approach 2:
The discrimination circuit provides feedback information about the type of fail detected, which feeds into the counting and correction processes. This feedback mechanism enables the system to adapt its error handling strategy based on the specific fail type, allowing both uniform ECC correction and targeted repair operations to function effectively.
Data Source
AI summary
A fail information control circuit may include: a comparison circuit configured to generate a comparison result signal by comparing read data and write data; a fail bit discrimination circuit configured to generate a first fail discrimination signal for discriminating a fail detected when the write data has a first value and a second fail discrimination signal for discriminating a fail detected when the write data has a second value, in response to the comparison result signal; and a fail bit counter configured to generate a first counting signal by counting the first fail discrimination signal and generate a second counting signal by counting the second fail discrimination signal.