Fail Memory Board Power Gating in Semiconductor Test Equipment
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Solution Overview
Problem
Semiconductor test apparatuses consume excessive power due to all functional units being activated regardless of test requirements, necessitating a need for efficient power management based on test circumstances.
Innovation Solution
A semiconductor test apparatus that powers off inactive functional units based on test mode and test target, utilizing a test management unit to determine test modes and control signals through AC-to-DC converters and interface boards to manage power distribution to fail memory boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all functional units are activated to ensure complete test functionality, then test capability and reliability are improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the power state of fail memory boards changeable based on test requirements. The system dynamically transitions fail memory boards between powered-on and powered-off states according to the current test mode, ensuring full functionality when needed while conserving power when not required.
Solution Approach 2:
The patent changes the power parameter of fail memory boards based on test mode. By adjusting the power state parameter from 'on' to 'off' depending on whether the test requires fail memory functionality, the system optimizes the balance between test capability and power consumption.
2Loss of energy
If fail memory boards are powered off to reduce power consumption, then power efficiency is improved, but test functionality may be compromised
Solution Approach 1:
The test management unit determines the current test mode and provides feedback control signals to power control units. This feedback mechanism ensures that fail memory boards are powered off only when the test mode does not require them, maintaining test functionality while improving power efficiency.
Solution Approach 2:
The system performs preliminary determination of test mode requirements before executing the test. The test management unit analyzes the test program to identify whether fail memory boards will be needed, and pre-adjusts their power state accordingly, avoiding unnecessary power consumption from the outset.
3Ease of operation
If the system automatically determines test mode by analyzing test programs, then ease of operation is improved, but device complexity increases
Solution Approach 1:
The test management unit automatically analyzes the test program itself to determine the required test mode and power requirements. This self-service approach eliminates the need for manual configuration, improving ease of operation despite the increased processing complexity within the test management unit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption by up to 20% by selectively powering off fail memory boards during post-repair tests, optimizing power usage according to test requirements.
Implementation Method 1
one or more alternating current (AC)-to-direct current (DC) converters (ADCs) connected to the fail memory boards
Data Source
AI summary
A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.