Fail-Safe Clock Buffer Frequency Deviation Detection
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Solution Overview
Problem
Modern communication networks face catastrophic failures due to loss or sudden changes in clock signals, making it difficult to recover or diagnose, as they rely on individual frequency control devices which are unreliable and costly.
Innovation Solution
A fail-safe clock generator with a monitor circuit and temperature-compensated LC oscillator that generates a short-term stable reference frequency, detects frequency deviations, and switches to a backup clock signal, using frequency-to-digital converters and logic circuits to manage input clock signals and provide fault detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single frequency controlled source is used for multiple subsystems, then cost is reduced, but reliability deteriorates due to catastrophic system failure risk
Solution Approach 1:
The patent implements preliminary action by continuously monitoring the frequency of the single frequency-controlled source before it can cause catastrophic failure. The monitor circuit detects frequency deviations in advance, allowing the system to switch to a backup oscillator or trigger protective actions before the single source failure propagates through all subsystems, thus maintaining reliability while using a cost-effective single source architecture.
Solution Approach 2:
The patent applies feedback by creating a closed-loop monitoring system where the monitor circuit continuously measures the frequency of the shared clock source and feeds this information back to control logic. This feedback mechanism enables real-time detection of frequency deviations and automatic system response, resolving the contradiction by making the single frequency-controlled source reliable through continuous surveillance and automatic correction/switching capabilities.
2Reliability
If frequency monitoring is implemented to detect small relative frequency changes, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex mechanical or analog frequency monitoring mechanisms with a digital implementation. The monitor circuit uses a frequency-to-digital converter to transform the analog frequency measurement into a digital value that can be easily processed by digital logic circuits. This substitution simplifies the overall monitoring system while enabling precise detection of small frequency changes, thus improving reliability without proportionally increasing complexity.
Solution Approach 2:
The patent changes the parameter domain for frequency monitoring by converting frequency (analog parameter) into a digital representation through frequency-to-digital conversion. This parameter transformation allows the use of simple digital comparators and logic circuits to detect frequency deviations, reducing the complexity of the monitoring circuit while maintaining high sensitivity to frequency changes, thereby resolving the contradiction between reliability improvement and complexity increase.
3Manufacturing precision
If temperature compensation is applied to maintain frequency accuracy, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex analog temperature compensation circuits with a digital implementation. A temperature sensor provides digital or easily processable temperature data to a digital processor that calculates and applies compensation values to the frequency-to-digital converter. This substitution maintains high frequency accuracy across temperature variations while using simpler, more integrated digital components, thus improving manufacturing precision without proportionally increasing overall device complexity.
Solution Approach 2:
The patent implements multi-functionality by integrating temperature compensation into the existing frequency monitoring and conversion circuitry. The same digital processor that handles frequency-to-digital conversion also performs temperature compensation calculations, and the compensation is applied within the same signal path. This universal approach maintains frequency accuracy across temperature ranges while avoiding the need for separate dedicated compensation hardware, thus improving manufacturing precision without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of output clock signals by continuously monitoring frequencies, reducing static frequency offsets, and detecting small relative frequency changes, thereby preventing system failures and improving accuracy through temperature compensation.
Implementation Method 1
The monitor circuit may include a temperature compensation circuit configured to temperature compensate a relative frequency measurement of the first frequency of the first input clock signal relative to the short-term stable reference frequency based on a digital sensed temperature and predetermined temperature coefficients describing a relationship between temperature and a corresponding frequency of the clock signal
Implementation Method 2
The oscillator circuit may be a temperature-compensated LC oscillator including a passive temperature compensation circuit configured to provide compensation to the temperature-compensated LC oscillator in response to a temperature change
Data Source
AI summary
Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.