Fail-Safe Pin Voltage Protection Circuit
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Solution Overview
Problem
In systems with shared fail-safe pins, a circuit block in power-down mode can still affect the settling time of other blocks, leading to undesired interactions and interference.
Innovation Solution
A modified fail-safe signal is generated that is asserted both when the voltage at the fail-safe pin is greater than VDD and when the circuit block is in power-down mode, preventing switching and thus eliminating interference with other circuit blocks without requiring a large additional switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fail-safe circuit is implemented to protect against voltage greater than VDD, then reliability is improved, but device complexity increases due to additional circuit blocks needed to manage shared pin interactions
Solution Approach 1:
The patent combines the fail-safe protection function with the power-down control function into a single integrated circuit block. The fail-safe circuit receives both the voltage monitoring signal and the power-down signal, and generates a single modified fail-safe signal that incorporates both protection functions. This merging eliminates the need for separate circuit blocks to handle shared pin interactions, thereby maintaining reliability while reducing device complexity.
2Object-affected harmful factors
If a large switch is added to prevent switching during power-down mode, then interference with other circuit blocks is eliminated, but device complexity and area increase
Solution Approach 1:
The patent introduces an intermediary modified fail-safe signal that mediates between the original fail-safe signal and the power-down control signal. This intermediate signal incorporates the power-down state information and uses it to control the switching behavior of the PMOS transistor. By using this intermediary signal instead of adding a large physical switch, the patent eliminates interference with other circuit blocks during power-down mode while avoiding the complexity and area overhead of additional large switching components.
3Loss of time
If the fail-safe signal is modified to account for power-down mode, then settling time of other blocks is maintained, but circuit complexity increases
Solution Approach 1:
The modified fail-safe signal serves multiple functions simultaneously: it provides voltage-over-VDD protection, it prevents switching during power-down mode, and it maintains settling time for other circuit blocks sharing the common pin. By designing a single modified signal that accomplishes all three functions, the patent maintains settling time performance without requiring separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.