Asynchronous Fail Signal Line for Memory Program Failure Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices often experience write/program failures due to worn-out or defective memory cells, leading to inefficiencies and operational delays, particularly when polling status registers is required for error detection, which can tie up the memory bus and slow down operations.
Innovation Solution
Implementing an asynchronous electronic fail signal to indicate program failures, allowing the controller or processor to manage failures without polling, thereby improving memory speed and efficiency by using a fail signal line with an open-collector configuration and a ready-busy signal line to indicate pending and completed operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polling status registers is used for error detection, then program failures can be detected, but the memory bus is tied up and operation speed decreases
Solution Approach 1:
The patent extracts the failure detection function from the polling process by implementing a dedicated fail signal line that independently indicates program failures. This separates the error detection mechanism from the main data bus operations, allowing failure detection without tying up the memory bus for polling status registers.
Solution Approach 2:
The patent introduces an intermediary fail signal line that acts as a dedicated communication channel between the memory device and controller for error indication. This intermediary mechanism enables reliable failure detection while avoiding the bottleneck of using the main data bus for status polling.
2Reliability
If polling status registers is used for error detection, then program failures can be detected, but operation efficiency decreases due to bus tie-ups
Solution Approach 1:
The patent extracts the failure detection function from the polling process by implementing a dedicated fail signal line that independently indicates program failures. This separates the error detection mechanism from the main data bus operations, allowing failure detection without tying up the memory bus for polling status registers.
Solution Approach 2:
The patent enables continuous memory operations by maintaining the data bus available for productive work while the fail signal line continuously monitors and reports errors independently. This ensures that error detection does not interrupt or slow down the main data processing operations.
3Quantity of substance
If multiple parallel non-volatile memory devices are used, then storage capacity increases, but the complexity of managing failures across devices increases
Solution Approach 1:
The patent merges the failure indication functions of multiple parallel memory devices onto a single shared fail signal line. This consolidation allows the controller to monitor all devices for errors through one unified interface, significantly simplifying failure management while maintaining support for multiple high-capacity devices.
Data Source
AI summary
Subject matter disclosed herein relates to a memory device and a method of operating same.