Failover Processor System Recovery via Instruction Set Translation
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Solution Overview
Problem
In computer systems with multiple processors, the failure of one processor can render the system inoperable for its intended purpose, even if the overall system remains operational, due to the loss of functionality provided by the failed processor.
Innovation Solution
Implementing a failover processor with a different instruction set that can execute operations normally handled by the failed processor, allowing the system to continue operating by switching to the failover processor in case of failure and ensuring system recovery through reinitialization and notification of the failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single processor is used in the computer system, then the device complexity is reduced, but the system reliability deteriorates because the entire system becomes inoperable if the processor fails
Solution Approach 1:
The patent merges the functionality of multiple processors into a unified failover configuration where a primary processor and backup processor work together as a single system. The backup processor remains in standby mode, ready to take over immediately if the primary processor fails, effectively combining their capabilities to ensure continuous operation without requiring complex multi-processor coordination during normal operation.
Solution Approach 2:
The patent implements beforehand cushioning by maintaining a backup processor in a ready state before any failure occurs. This backup processor is pre-configured with the necessary instructions and capabilities to immediately assume the role of the primary processor, providing a cushion against system failure and ensuring business continuity without interruption to the point of sale operations.
2Reliability
If multiple processors are used in the computer system, then the system reliability is improved, but the device complexity increases due to the need for failover mechanisms and instruction set compatibility
Solution Approach 1:
The patent applies universality by designing the backup processor with multi-functional capability to execute instructions from different instruction sets. The backup processor can natively execute its own instruction set and also execute instructions from the primary processor's instruction set through translation or emulation, making it a universal processor that can fulfill multiple roles and reducing the need for separate specialized processors.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of an instruction translation layer or emulation software that enables communication and compatibility between processors with different instruction sets. This intermediary allows the backup processor to understand and execute instructions from the primary processor, simplifying the failover process and reducing the complexity of direct multi-processor coordination.
3Adaptability or versatility
If a backup processor with a different instruction set is used, then the adaptability of the system is improved, but the ease of operation deteriorates due to instruction translation requirements
Solution Approach 1:
The patent applies preliminary action by pre-translating or pre-loading the necessary instruction set compatibility layers into the backup processor before failover occurs. The backup processor is pre-configured with the ability to execute both its native instruction set and the primary processor's instruction set, so that when failover occurs, no real-time translation is needed and operations continue seamlessly without performance degradation.
Data Source
AI summary
Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.