Failsafe Clock Source Switching for Low-Jitter Holdover

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Solution Overview

Problem

Existing clock synchronization technologies, such as GPS and Precision Time Protocol (PTP), face issues with reliability and accuracy due to time offsets, short-term errors, and unavailability of GPS signals, leading to unstable output clock signals with low-frequency drift and high jitter, which are unacceptable for precise timing applications.

Innovation Solution

A clock product that generates quality determinations for reference clock signals using frequency metrics, selectively locks to active clock signals based on quality, and switches to alternate signals when quality metrics are not met, employing cascaded phase-locked loops and holdover techniques to maintain frequency stability and reduce jitter.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If GPS time signals are used for clock synchronization, then clock accuracy is improved on average, but GPS signals may be unavailable or erroneous over short time periods

Engineering Contradiction:
Improveclock accuracyVSAvoidsignal availability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The system performs preliminary frequency estimation and quality assessment of multiple clock sources before GPS signal failure occurs. By pre-evaluating the stability and accuracy of backup clock sources (such as OCXO, TCXO, or local oscillators), the system is prepared to switch to the most suitable alternative when GPS becomes unavailable, minimizing timing disruptions and maintaining synchronization accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements a cushioning mechanism by maintaining multiple clock sources with different characteristics (high-stability OCXO, medium-stability TCXO, and local oscillators) ready as backups. This creates a buffer against GPS signal failure, ensuring that when the primary GPS signal becomes unavailable or erroneous, the system can immediately transition to a pre-prepared alternative source, thereby maintaining continuous reliable operation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If multiple clock sources are monitored and switched between, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveclock signal reliabilityVSAvoidclock source management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system employs feedback mechanisms through frequency estimation modules that continuously monitor the quality and stability of each clock source. Quality metrics are calculated based on frequency deviation and stability measurements, and this feedback information is used by the controller to automatically select and switch between clock sources. This closed-loop feedback system simplifies the management complexity by providing automated, data-driven decision-making for clock source selection.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The clock synchronization system performs self-service by automatically evaluating multiple clock sources, determining their relative quality through frequency estimation, and selecting the best source without external intervention. The system autonomously monitors its own performance, detects degradation or failure in any clock source, and switches to alternatives based on pre-established quality criteria, thereby managing its own reliability without requiring complex external control.

Inventive Principle:
Principle #25Self-service

3Reliability

If holdover mode is implemented to maintain clock signal during GPS failure, then reliability is improved, but low-frequency drift increases

Engineering Contradiction:
Improvecontinuous clock operationVSAvoidfrequency stability
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

Before entering holdover mode, the system performs preliminary frequency estimation and characterizes the drift characteristics of available backup clock sources. By pre-assessing the frequency stability and drift rates of OCXO, TCXO, and local oscillator sources, the system can predict which backup source will maintain the best frequency accuracy during the anticipated holdover period, allowing for optimized selection that minimizes low-frequency drift while ensuring continuous operation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10483987B1Failsafe clock product using frequency estimation
Publication Date: 2019.11.19 SKYWORKS SOLUTIONS INC
  • US10483987B1 patent drawing
  • US10483987B1 patent drawing
  • US10483987B1 patent drawing

AI summary

A method for operating a clock product includes generating a quality determination for a reference clock signal based on frequency metrics for a plurality of independent clock signals. The frequency metrics are generated using the reference clock signal. The method includes generating an output clock signal by locking to an active clock signal selected from the plurality of independent clock signals in response to the quality determination satisfying a predetermined quality metric. For each input clock signal of the plurality of independent clock signals, the frequency metrics include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts, and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.