Fail-Safe Counter Evaluation Using Synchronized Test Pulses
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Solution Overview
Problem
There is a need for a method to ensure proper counting operations in fail-safe counters, as existing technologies lack effective evaluation methods to prevent missed or extraneous counts, which can lead to system malfunctions and safety issues.
Innovation Solution
A fail-safe counter evaluator system using two counters, where one counter is driven by externally generated pulses and the other receives test pulses for evaluation, ensuring synchronization and proper operation by alternating testing between the counters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a counter is used to count pulses in a digital circuit, then the counting function is achieved, but there is no mechanism to detect missed counts or extraneous counts, leading to potential system failures
Solution Approach 1:
The counter system is segmented into multiple independent counters (first counter and second counter) that operate in parallel. Each counter independently processes count pulses, allowing for redundancy and failure detection without requiring a complete redesign of the counting mechanism.
Solution Approach 2:
The invention implements a feedback mechanism where the output of one counter is fed back to control the operation of another counter. Specifically, when the first counter reaches a predetermined value, it generates a feedback signal to reset or control the second counter, enabling continuous monitoring and detection of counting errors.
2Measurement precision
If a fail-safe counter evaluation method is implemented to detect counting errors, then counting accuracy is improved, but the system complexity and number of components increase
Solution Approach 1:
The evaluation function is merged with the counting function by using the same counter components to perform both counting and self-evaluation. The counters serve dual purposes: counting input pulses and simultaneously evaluating each other's counting accuracy through cross-comparison, eliminating the need for separate evaluation hardware.
Solution Approach 2:
The counter system performs self-evaluation by using its own components to monitor and verify counting accuracy. Each counter serves itself and the other counter through mutual verification, where the first counter evaluates the second counter and vice versa, reducing the need for external evaluation systems.
3Reliability
If multiple counters are used for mutual evaluation, then counting reliability is improved, but the device complexity and component count increase
Solution Approach 1:
Each counter in the system is designed to be universal, performing multiple functions: counting input pulses, being evaluated by another counter, and evaluating the other counter. This multi-functionality allows the same counter components to serve multiple purposes, reducing the overall system complexity despite having multiple counters.
Solution Approach 2:
The counter evaluation operates periodically based on predetermined count values. When a counter reaches a specific threshold value, it triggers an evaluation cycle where the counters exchange verification signals. This periodic action allows for continuous monitoring without requiring constant evaluation, optimizing the balance between reliability and resource usage.
Data Source
AI summary
A fail-safe counter evaluator is provided to insure proper counting operations by fail-safe counters. The failsafe counter evaluator comprises a first microprocessor, a first counter, a second counter, a second microprocessor and a test channel. The first counter is configured as a counter in operation and disposed in the first microprocessor to receive externally generated count pulses. The second counter is disposed in the first microprocessor and configured to undergo a test. The test channel is configured to send an input test signal to the second counter based on test pulses from the second microprocessor. The first microprocessor and the second microprocessor are synchronized so that to coordinate a start and an end of the test. The second counter is evaluated after the test pulses have been sent to determine if the second counter is operating properly.


