Fail-Safe IO Circuit Cutoff for Glitch-Free Power Transitions
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Solution Overview
Problem
Integrated circuits (ICs) face issues with high leakage currents when IO circuits are not properly tri-stated during power transitions, leading to glitches and the need for frequent re-initialization of memory devices like DDR3 SDRAM, which increases power consumption and reduces reliability.
Innovation Solution
An IO circuit design that includes a cutoff circuit and an output stage, coupled with a pad, maintains the pad voltage at logic high during IO supply voltage transitions below a defined threshold, preventing leakage currents and ensuring fail-safe operation by tri-stating the output stage before the supply voltage drops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the IO circuit is not properly tri-stated during power transitions, then the power consumption is reduced, but high leakage currents flow from the pad into the IO circuit causing glitches
Solution Approach 1:
The cutoff circuit is activated before the IO supply voltage transitions to prevent leakage currents. The circuit detects the voltage transition threshold and proactively tri-states the output stage, ensuring the pad is properly isolated before the actual power down occurs, thus preventing glitches while maintaining low power consumption
Solution Approach 2:
The cutoff circuit acts as an intermediary between the pad and the IO circuit internal structure. It provides a controlled isolation mechanism that prevents direct leakage current paths while allowing the IO circuit to be properly tri-stated during power transitions, resolving the conflict between power consumption and signal integrity
2Loss of energy
If the IO supply voltage is powered down while the pad is held at logic-HIGH, then power consumption is reduced, but leakage currents flow from the pad to the IO circuit
Solution Approach 1:
The cutoff circuit applies a counter-action before the harmful leakage current can occur. When the IO supply voltage begins to transition, the cutoff circuit preemptively blocks the current path from the pad to the IO circuit internal nodes, preventing the formation of leakage current even when the pad is held at logic-HIGH
Solution Approach 2:
The harmful leakage current path is extracted or removed from the system by activating the cutoff circuit. The cutoff transistor effectively disconnects the pad from the IO circuit internal structure, eliminating the leakage current path while allowing the IO supply to be powered down
3Reliability
If the RESET pin undergoes a glitch during power transitions, then the DDR3 SDRAM is reset, but frequent re-initialization increases power consumption and reduces reliability
Solution Approach 1:
The cutoff circuit prevents the glitch condition before it can occur by proactively tri-stating the IO circuit output stage during power transitions. This preliminary action ensures the RESET pin voltage remains stable and prevents unwanted DDR3 SDRAM resets, maintaining memory content integrity while avoiding the power consumption associated with frequent re-initialization
Data Source
AI summary
The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.