Failsafe Pass Gate Circuit for Bus-Powered-Down Isolation
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Solution Overview
Problem
Conventional pass gate circuits experience a low impedance path between input and output terminals during bus-powered-down conditions, leading to unwanted signal propagation and errors when the supply voltage is zero, as there is no high potential voltage at the gate of P-channel MOSFETs, causing current to leak through the switch.
Innovation Solution
Incorporating a failsafe circuit with a failsafe inverter powered by the input signal, which controls the P-channel MOSFETs to create a high-impedance path between the input and output terminals, ensuring that the P-channel MOSFETs are turned off even when the supply voltage fails, thereby preventing signal propagation and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pass gate circuit is operated during bus-powered-down condition, then the circuit can handle zero supply voltage, but a low impedance path is created between input and output terminals causing unwanted signal propagation
Solution Approach 1:
The failsafe inverter is configured to activate in advance when supply voltage drops, proactively turning on the P-channel MOSFET to create a high-impedance path before unwanted signal propagation can occur. This preliminary action prevents the harmful effect rather than reacting to it after it occurs.
Solution Approach 2:
The P-channel MOSFET acts as an intermediary element that can be dynamically controlled to switch between conducting and blocking states. By introducing this controllable intermediary, the circuit can maintain signal isolation during bus-powered-down conditions while still allowing normal operation when supply voltage is present.
2Device complexity
If conventional pass gate circuit is used without failsafe circuit, then the device complexity is low, but current leakage occurs from input to output during supply voltage failure
Solution Approach 1:
The P-channel MOSFET serves as a controllable intermediary element inserted into the signal path. When activated by the failsafe inverter during supply voltage failure, it blocks current leakage between input and output terminals. This intermediary provides precise control over current flow without significantly complicating the overall circuit structure.
Solution Approach 2:
The invention changes the impedance parameter of the signal path by dynamically switching the P-channel MOSFET between on and off states. During normal operation, the MOSFET is off allowing signal passage. During supply voltage failure, the MOSFET turns on to create a high-impedance path, changing the electrical characteristics to prevent current leakage.
3Device complexity
If the P-channel MOSFET gate is not controlled during supply voltage failure, then the control circuit is simple, but incorrect signals are propagated to external systems
Solution Approach 1:
The failsafe inverter creates a feedback mechanism that monitors the supply voltage status and automatically adjusts the P-channel MOSFET gate control accordingly. When supply voltage fails, the inverter detects this condition and activates the MOSFET to block signal propagation, ensuring external systems receive correct high-impedance states rather than incorrect signals.
Solution Approach 2:
The failsafe inverter acts as an intermediary control element between the supply voltage and the P-channel MOSFET gate. It translates supply voltage status into appropriate gate control signals, ensuring that the MOSFET is properly controlled during supply voltage failure without requiring complex control circuitry.
Data Source
AI summary
A pass gate circuit arranged for providing an input to an output based on a control signal, the pass gate circuit including a pass gate switch circuit including a P-Metal Oxide Semiconductors (PMOS) Field Effect Transistor (FE), PMOS FET, cascaded in parallel with an NMOS FET, the pass gate switch circuit is arranged to provide the input to the output, and includes a control circuit including two in series cascaded inverters, an output of a first of the two inverters is provided to a gate of the PMOS FET and an output of a second of the two inverters is provided to a gate of the NMOS FET, and the inverters are powered by a supply voltage.