Fail-Safe Switch Circuit for High-Speed ADCs With Zero Quiescent Current
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) face challenges in achieving low impedance and low power consumption, particularly in battery-powered devices, where existing switches often require high quiescent current and cannot operate reliably at high frequencies due to conflicts between high data rates, low power requirements, and failsafe operations.
Innovation Solution
A circuit design incorporating a switch with n-channel and p-channel field effect transistors, a voltage generation circuit, a level shifter, and a logic unit that generates a secondary signal to control the transistors, allowing for high-speed operation with low impedance and zero quiescent current by automatically switching between voltages and ensuring failsafe operation without static current draw.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional switches are used in high-speed ADCs, then high data rates can be achieved, but power consumption increases due to high quiescent current requirements
Solution Approach 1:
The switch uses periodic clocked control signals to activate transistors only during required sampling intervals, replacing continuous DC biasing. The control circuit generates periodic clock phases that turn transistors on and off, eliminating continuous quiescent current while maintaining high-speed operation during active sampling periods.
Solution Approach 2:
The invention dynamically changes transistor operating parameters by using clocked control signals to modulate gate voltages. Transistors switch between cutoff and active regions periodically, changing their electrical characteristics to achieve low power during idle states while maintaining high-speed performance during active sampling.
2Speed
If switches operate at high speed with low impedance, then high data rates are achieved, but power consumption increases
Solution Approach 1:
The switch circuit uses periodic clocked control to activate transistors only during required sampling intervals. Multiple clock phases control different transistor groups sequentially, enabling high-speed switching when needed while eliminating continuous power dissipation during idle periods.
Solution Approach 2:
The invention makes the switch characteristics dynamic by using clocked control signals that continuously adjust transistor operating states. The switch transitions between high-impedance/low-power and low-impedance/high-speed states dynamically, rather than maintaining fixed DC bias conditions.
3Productivity
If battery-powered portable devices use high-speed ADCs, then high performance is achieved, but battery life decreases due to high power consumption
Solution Approach 1:
The switch circuit employs periodic clocked control to activate transistors only during required sampling intervals. This intermittent operation mode enables high-performance ADC conversion when needed while dramatically reducing average power consumption for battery-powered portable devices.
4Device complexity
If conventional switches are used, then simple circuit structure is maintained, but failsafe operation cannot be ensured when input signal exceeds supply voltage or reaches zero volts
Solution Approach 1:
The invention introduces a control circuit as an intermediary between the input signal and the switch transistors. This control circuit monitors input voltage levels and adjusts transistor gate voltages accordingly, preventing harmful voltage conditions while maintaining simple overall circuit structure.
Solution Approach 2:
The control circuit provides beforehand protection by monitoring input signals and preemptively adjusting transistor operating states to prevent damage from voltage excursions. The circuit cushions against harmful voltage conditions before they can affect the switch transistors, ensuring reliable operation across extended voltage ranges.
Data Source
AI summary
In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.