Failure Address Cache Routing for Stacked Memory Die Repair
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Solution Overview
Problem
Existing wafer-on-wafer stacking techniques for stacked memory devices, such as DRAM, fail to effectively select good dies for stacking, leading to unrepaired failed dies and reduced yield.
Innovation Solution
Incorporating a spare die with a failure address cache that records and manages failure address information to repair target memory dies by controlling access based on hit or miss signals, allowing or blocking access to memory arrays as necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer-on-wafer stacking technique is used to stack logic wafer and memory wafers, then stacked memory can be formed, but good dies cannot be selected and failed dies cannot be repaired
Solution Approach 1:
The invention divides the memory device into functional segments: a plurality of memory dies (D0-D3) and a separate spare die (DS). This segmentation allows independent selection and testing of each die, enabling the spare die to be designated specifically for repair operations while memory dies are selected for stacking, thus resolving the contradiction between stacking efficiency and die selection flexibility.
Solution Approach 2:
The failure address cache acts as an intermediary mechanism between the address signal and the memory array access control. It receives address signals, compares them with stored failure addresses, and generates hit/miss signals that mediate the access control logic, enabling intelligent routing of read/write operations to avoid failed dies while maintaining stacking efficiency.
2Ease of manufacture
If failed die in stacked memory is not repaired, then stacking process is simple, but yield of stacked memory is reduced
Solution Approach 1:
The failure address cache is pre-configured with failure address information before the memory device is put into operation. This preliminary action enables the system to identify and avoid failed dies during normal operation without complicating the stacking manufacturing process, thus maintaining ease of manufacture while improving yield through proactive failure avoidance.
Solution Approach 2:
The invention effectively discards failed dies by routing their address spaces through the failure address cache, which redirects access requests away from defective memory regions. This allows the system to recover usable functionality from what would otherwise be defective devices, thereby improving yield without adding complex repair hardware during manufacturing.
3Device complexity
If access to memory array is not controlled based on failure address cache, then access control logic is simple, but failed bank groups, banks and rows cannot be efficiently repaired
Solution Approach 1:
The failure address cache implements a feedback mechanism where failure address information is stored and compared with incoming address signals. The cache outputs hit/miss signals that provide feedback to the access control logic, enabling dynamic adjustment of read/write operations based on real-time failure detection, thus improving repair efficiency without excessive complexity.
Solution Approach 2:
The access control logic becomes dynamic through the failure address cache's hit/miss signals. Instead of static access control, the system adaptively routes address signals based on whether they correspond to failed or functional memory regions, enabling efficient repair operations while maintaining manageable control logic through the cache's automated comparison function.
Data Source
AI summary
A memory device includes a plurality of memory dies and a spare die that is stacked to the memory dies and is configured to repair a target memory die among the plurality of memory dies. Each of the spare die and the memory dies may include a failure address cache that records failure address information of the memory device. The failure address cache is configured receive an input address signal and output a hit signal or a miss signal, indicating a hit or a miss of the input address signal with failed addresses stored in the failure address cache. The memory device is configured to control an access to the memory dies and the spare die according to the hit signal or the miss signal.