Failure Analysis Method for Yield Enhancement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional failure analysis techniques for electronic devices with error correction circuitry are inefficient as they do not account for error correction capabilities, leading to unnecessary device rejection and reduced manufacturing yield.
Innovation Solution
A method and apparatus that utilize a processor and memory to store error information in a table, determining the number of bit positions that failed during testing, and assess whether the device passed or failed based on error correction thresholds, allowing for real-time analysis and increased yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional failure analysis techniques are used that do not account for error correction capabilities, then testing is simpler to implement, but manufacturing yield is reduced due to unnecessary device rejection
Solution Approach 1:
The patent applies preliminary action by pre-configuring the test system with knowledge of the device's error correction capabilities (e.g., single-bit ECC, double-bit ECC) before testing begins. This allows the testing methodology to be adapted in advance to account for correctable error patterns, preventing false failures and improving manufacturing yield without adding complex post-processing analysis
Solution Approach 2:
The patent changes the testing parameters by modifying how test results are evaluated based on the device's error correction characteristics. Instead of treating all errors as failures, the system adjusts the failure criteria to distinguish between correctable and uncorrectable errors, thereby reducing unnecessary device rejection while maintaining testing effectiveness
2Measurement precision
If post-processing analysis is performed by stepping through patterns one at a time to replicate and analyze each error, then failure analysis is more thorough, but testing time and cost increase significantly
Solution Approach 1:
The patent extracts the error analysis function from the sequential post-processing workflow and integrates it into the real-time testing process. By capturing and analyzing error patterns during the initial test execution rather than requiring separate post-processing steps, the system achieves thorough failure analysis without the time penalty of stepping through patterns individually
Solution Approach 2:
The patent maintains continuity of useful action by performing failure analysis concurrently with test execution rather than interrupting the process for post-processing. The system continuously monitors test results and applies error correction logic in real-time, eliminating idle time and maintaining productive workflow while delivering comprehensive failure analysis
Data Source
AI summary
In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred in the device and storing a bit position of each failed bit corresponding to that address; for each unique address at which at least one error occurred, determining how many different bit positions corresponding to the address failed during the test series; and based on results of the test series, determining whether the device failed the test series.