Failure Detection Circuit for Semiconductor Devices

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Solution Overview

Problem

Existing failure diagnosis circuits for semiconductor devices in vehicles and industrial machines face challenges in reducing circuit scale while effectively detecting failures, especially when the device is not in operation, leading to potential secondary damages and increased complexity.

Innovation Solution

A failure detection circuit comprising EXOR gates, a low-frequency signal generator, and a comparator that generates periodic signals to detect mismatches in signal levels, allowing for failure detection without the need for duplicated circuits or software diagnosis, thereby reducing circuit scale and enabling detection even when the device is not operating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If duplicated circuits or software diagnosis are used for failure detection, then failure detection capability is improved, but circuit scale and complexity increase

Engineering Contradiction:
Improvefailure detection capabilityVSAvoidcircuit scale
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

An intermediary signal generation circuit is introduced that creates a reference signal independent of the I/O control module. This reference signal is XORed with the actual I/O signal to detect failures without duplicating the entire I/O control circuitry. The intermediary circuit acts as a mediator between the I/O module and the detection logic, enabling failure detection with minimal added complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Instead of duplicating the entire I/O control circuit, the invention creates a simplified copy in the form of a signal generation circuit that produces expected signal patterns. This lightweight copy is sufficient for detection purposes and when combined with XOR logic provides failure detection capability without the full complexity of circuit duplication.

Inventive Principle:
Principle #26Copying

2Device complexity

If failure detection is implemented only during operation, then circuit complexity is reduced, but failure detection is impossible when device is not operating

Engineering Contradiction:
Improvecircuit complexityVSAvoidfailure detection coverage
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The signal generation circuit produces periodic test signals even when the I/O control module is not operating. By continuously generating these reference signals and XORing them with the I/O signals, the system can detect failures in the signal paths regardless of whether the main device is actively processing data. This periodic signal generation ensures continuous monitoring capability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The failure detection mechanism is prepared in advance by setting up the signal generation circuit and XOR comparison logic before actual operation begins. This preliminary configuration allows the system to detect failures that occur during idle states or between operational periods, ensuring comprehensive coverage without requiring complex operational state management.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11639961B2Failure detection circuit and semiconductor device
Publication Date: 2023.05.02 KK TOSHIBA
  • US11639961B2 patent drawing
  • US11639961B2 patent drawing
  • US11639961B2 patent drawing

AI summary

A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.