Fair Ready Scheduler for Multi-Thread Processor Throughput
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Solution Overview
Problem
Existing CPU microarchitectures face challenges in applying highly multi-threaded designs to common off-the-shelf servers for scale-out software, leading to high overhead and inefficiency in performance, silicon area, and power consumption, while maintaining compatibility with industry-standard instruction sets.
Innovation Solution
A fair ready scheduler is implemented with a tree structure or ready round-robin mechanism to select instructions from multiple hardware threads, ensuring fairness and reducing wasted cycles by selecting only ready instructions, thereby improving throughput and utilization efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If out-of-order microarchitecture is used to improve instruction execution speed, then single hardware thread performance increases, but silicon area and power consumption increase due to extra logic gates
Solution Approach 1:
The processor is divided into multiple hardware threads (e.g., 8 threads) that share common execution resources. Each thread has its own instruction fetch unit and register file, but they share execution units, memory ports, and scheduling logic. This segmentation allows parallel instruction execution while reducing per-thread hardware footprint, thereby decreasing total silicon area compared to traditional out-of-order designs.
Solution Approach 2:
The execution units and memory subsystems are designed to be universal and shared across multiple hardware threads. The same execution unit can process instructions from any thread, and the memory ports are multiplexed to serve multiple threads. This multi-functionality eliminates the need for dedicated execution resources for each thread, reducing overall silicon area while maintaining high throughput.
2Speed
If out-of-order microarchitecture is used to improve instruction execution speed, then single hardware thread performance increases, but power consumption increases due to extra logic gates
Solution Approach 1:
By segmenting the processor into multiple threads that share execution resources, the patent reduces the total number of active logic gates required. Instead of each thread having dedicated out-of-order execution infrastructure, the shared resources are activated only when needed, reducing overall power consumption while maintaining high instruction execution speed through parallelism.
Solution Approach 2:
The scheduler dynamically selects which hardware thread executes next based on instruction readiness and system state, rather than using static thread scheduling. This dynamic selection allows the system to activate only the necessary execution resources for currently ready instructions, reducing power consumption compared to continuously active out-of-order execution units.
3Device complexity
If traditional scheduling methods are used to select instructions from multiple hardware threads, then implementation is simple, but throughput and utilization efficiency decrease due to unfair scheduling and wasted cycles
Solution Approach 1:
The scheduler uses a round-robin approach with priority levels that cycles through hardware threads in a periodic manner. Each thread gets a turn to execute at each priority level, ensuring fair time sharing. This periodic scheduling pattern simplifies the scheduler implementation while improving throughput by preventing any single thread from monopolizing execution resources and reducing wasted cycles from unfair scheduling.
Solution Approach 2:
The scheduler ensures continuous useful action by always selecting a ready instruction from a hardware thread when execution units are available. The fair scheduling mechanism guarantees that all ready threads have equal opportunity to execute, eliminating idle cycles and maximizing utilization efficiency while maintaining relatively simple implementation through priority-based turn-taking.
4Productivity
If highly multi-threaded microarchitecture is applied to common servers, then performance can improve, but compatibility with industry-standard instruction sets becomes difficult to maintain
Solution Approach 1:
The processor implements a universal instruction set architecture that supports both industry-standard instructions (x86, ARM, RISC-V) and custom high-performance instructions. The execution units are designed to be instruction-agnostic, with a unified decoding and execution framework that can handle multiple instruction sets. This universality allows the highly multi-threaded architecture to maintain compatibility with existing software while achieving improved performance through parallel execution.
Solution Approach 2:
The processor dynamically adapts its microarchitectural parameters based on the instruction type being executed. Different instruction sets and instruction types trigger different microarchitectural behaviors in the execution units, allowing the same hardware to efficiently execute both standard and custom instructions. This parameter adaptation enables high performance for scale-out workloads while maintaining broad instruction set compatibility.
Data Source
AI summary
A multi-thread processor can include logic that can be implemented in a form of physical logic gates, a plurality of hardware threads, one or more execution units that can execute one or more instructions, a least a level 1 cache that can be for data, and selection logic. Each hardware thread of the plurality of hardware threads can fetch instructions from a software thread of execution assigned to a corresponding hardware thread of the plurality of hardware threads. The selection logic can include one or more fair ready-schedulers. Each fair ready-scheduler of the one or more fair ready-schedulers can select instructions that are ready for execution from among the plurality of hardware threads. A distribution of which a hardware thread is chosen can be consistent with a pattern expected from choosing a ready instruction according to a uniform probability distribution.