Falling-Edge JTAG Router for Fast Board-Level Access
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Solution Overview
Problem
Existing JTAG router technologies either lengthen access time to JTAG device strings or require complex and costly encoding/decoding processes, and do not efficiently address individual boards in a system without modifying existing JTAG pattern sets.
Innovation Solution
A JTAG router device that operates on the falling edge of the TCK signal, allowing simplified access to JTAG device strings without extending access time or requiring complex encoding/decoding, using a Falling Edge Router (FER) with a simplified Falling Edge Controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional JTAG router technologies are used to address individual boards in a system, then board-level access capability is improved, but access time is lengthened and device complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring the JTAG router with board address registers and device string selection registers that are loaded during idle states. This allows the router to be ready for immediate board access without adding access time during active JTAG operations, as the routing configuration is prepared in advance during system idle periods
Solution Approach 2:
The patent applies segmentation by dividing the JTAG router functionality into separate components: board address registration logic, device string selection logic, and routing switch fabric. This segmentation allows each component to operate independently and efficiently, with the board address register handling board identification, the device string register handling device selection, and the switch fabric handling signal routing, thereby maintaining fast access times while providing board-level addressing capability
2Adaptability or versatility
If complex encoding/decoding processes are implemented in JTAG routers, then routing flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the complex encoding/decoding functionality from the JTAG router and replaces it with simple register-based address matching and direct routing. Instead of implementing Manchester-like encoding/decoding circuits, the patent uses straightforward board address registers that compare input addresses with stored board addresses, and device string selection registers that directly control the routing switch fabric, thereby achieving routing flexibility without complex encoding/decoding processes
Solution Approach 2:
The patent employs simple, cost-effective routing logic that uses basic digital comparators and multiplexers instead of complex encoding/decoding circuits. The board address registration and device string selection use standard logic elements that are inexpensive and easy to implement, providing adequate routing flexibility through simple address-matching and switch-fabric control mechanisms
3Reliability
If existing JTAG pattern sets are used without modification, then compatibility is maintained, but ability to address individual boards is lost
Solution Approach 1:
The patent implements dynamics by making the JTAG router configuration changeable during system operation. The board address registers and device string selection registers can be dynamically loaded and reconfigured without requiring changes to existing JTAG pattern sets. This allows the router to adapt to different board configurations and addressing requirements while maintaining compatibility with standard JTAG operations, as the routing logic dynamically responds to address inputs without requiring pattern modification
Data Source
AI summary
A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.