Falling-Edge Modulation Signal Receiver for HDMI eARC
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Solution Overview
Problem
The HDMI eARC system's PN mismatch configuration and DC-bias voltage difference cause duty cycle shifts in falling-edge modulation signals, leading to erroneous sampling results in the eARC-RX.
Innovation Solution
A falling-edge modulation signal receiver and sampling method utilizing a phase-locked loop, oversampling circuit, and decision circuit to generate an oversampling clock, sample the signal into groups of data, and analyze these data groups to accurately determine bit values, even under PN mismatch conditions, by using an oversampling frequency at least five times the signal clock frequency and determining bit values based on predetermined conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If sampling is performed at the middle of each cycle of the falling-edge modulation signal, then the bit value determination is simplified, but the duty cycle shift caused by PN mismatch and DC-bias voltage difference leads to erroneous sampling results
Solution Approach 1:
The patent applies preliminary action by performing oversampling at multiple points before the final bit value determination. The receiver samples the signal at N≥5 different time points within each bit cycle, allowing it to capture the signal characteristics before the duty cycle shift affects the sampling accuracy. This preliminary oversampling enables the system to compensate for the PN mismatch and DC-bias voltage difference effects.
Solution Approach 2:
The patent changes the sampling parameters by increasing the sampling frequency to N times the signal clock frequency (N≥5). This parameter change transforms the single-sample approach into an oversampling approach, where multiple samples are taken per bit cycle. The system then determines the bit value based on the distribution of these N samples, making the determination robust against duty cycle shifts caused by PN mismatch and DC-bias voltage differences.
2Productivity
If the eARC-RX samples the falling-edge modulation signal at a single point in time, then the sampling process is simple and fast, but the duty cycle shift causes erroneous sample results
Solution Approach 1:
The system performs preliminary oversampling at N≥5 different time points within each bit cycle before making the final bit value determination. This preliminary action captures the signal characteristics across the entire bit cycle, allowing the system to identify the correct bit value even when the duty cycle shifts due to PN mismatch and DC-bias voltage difference. The oversampling results are then processed to determine the final bit value, maintaining both speed and precision.
Solution Approach 2:
The patent implements a feedback mechanism where the N oversampled values are analyzed to determine the bit value. The system uses the distribution and pattern of these N samples as feedback to compensate for the duty cycle shift. By examining how the sampled values distribute across the bit cycle, the receiver can accurately determine the bit value despite the timing shifts caused by PN mismatch and DC-bias voltage differences.
Data Source
AI summary
A falling-edge modulation signal receiver is configured to process an input signal having a duty cycle varying with a bit value of the input signal. The receiver includes: a phase-locked loop for generating an oversampling clock according to the input signal which correlates with a signal clock, wherein the oversampling frequency is not lower than five times the frequency of the signal clock; an oversampling circuit for sampling the input signal according to the oversampling clock and thereby generating multiple groups of data which as a whole is corresponding to a single bit of the input signal; and a decision circuit for ascertaining that X bits of the multiple groups of data are 1 and determining the value of the single bit according to the X. When the X is greater/less than a threshold, the decision circuit determines that the value of the single bit is 1/0.