Phase Frequency Detector Using Falling Edges for Fast PLL Relock
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Solution Overview
Problem
Traditional phase frequency detectors (PFDs) in phase lock loop (PLL) circuits are inadequate in quickly regaining lock when a reference clock experiences sudden phase or frequency changes, especially when the phase delta exceeds 180 degrees, due to their limited ability to track both rising and falling edges of the signals.
Innovation Solution
A novel PFD design that tracks both the rising and falling edges of the reference clock and feedback signals, using logic circuitry to detect phase deltas greater than 180 degrees and adjust the up or down signals accordingly, allowing for faster lock recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a traditional phase frequency detector is used in a PLL circuit, then the circuit structure is simple, but the lock recovery time is long when phase delta exceeds 180 degrees
Solution Approach 1:
The PFD circuit is segmented into multiple independent paths: a first path tracking rising edges and a second path tracking falling edges. Each path has its own D flip-flops and logic gates. This segmentation allows the circuit to handle large phase deltas (>180 degrees) more effectively by detecting phase differences in both directions, thereby reducing lock recovery time without excessive complexity increase.
Solution Approach 2:
The invention adds a temporal dimension to phase detection by tracking both rising and falling edges of clock signals. Traditional PFDs only track rising edges (one dimension), while this invention utilizes both rising and falling edges (two dimensions in time), enabling detection of phase differences greater than 180 degrees and significantly improving lock recovery performance.
2Measurement precision
If the PFD tracks only rising edges, then the circuit complexity is low, but the ability to detect large phase deltas (>180 degrees) is limited
Solution Approach 1:
The phase detection function is segmented into two independent tracking paths: one for rising edges and one for falling edges. Each path uses dedicated D flip-flops (first and second for rising, third and fourth for falling) and associated logic gates. This segmentation enables precise measurement of phase differences in both directions, achieving accurate detection of large phase deltas while keeping each segment's complexity manageable.
Solution Approach 2:
The PFD circuit is designed with multi-functionality to track both rising and falling edges of clock signals. The first and second D flip-flops track rising edges, while the third and fourth D flip-flops track falling edges. This universal edge-tracking capability allows the circuit to accurately measure phase differences regardless of direction, significantly improving measurement precision for large phase deltas.
Data Source
AI summary
A variety of applications can include a phase frequency detector structured to track the falling edges of two input signals to detect a phase difference between the two signals and to generate one or more signals that can be used to adjust one of the signals with respect to the other when the phase difference is greater than 180 degrees. The phase frequency detector can be implemented in a phase lock loop circuit to track the falling edges of a reference clock signal and the falling edge of a feedback signal. In response to detection of the phase difference between the reference clock signal and the feedback signal being greater than 180 degrees using the falling edges of these signals, the phase frequency detector can adjust its output signals to provide for recovery of a lock condition for the reference clock signal. Additional devices, systems, and methods are discussed.