False Sharing Detection via Selective Cache Line Instrumentation
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Solution Overview
Problem
False sharing in multithreading environments leads to performance degradation due to frequent cache line invalidations, especially in systems with multiple cores or larger cache line sizes, as changes made by one core invalidate cache copies on other cores, causing unnecessary re-fetching from main memory.
Innovation Solution
A method and system for detecting false sharing by performing optimization passes on source code, adding instrumentation to track memory access addresses and types of global and heap variables, and using a runtime system to analyze cache invalidations, allowing for selective instrumentation and threshold-based tracking to reduce memory overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache line level coherency is implemented to ensure data consistency across cores, then data correctness is maintained, but performance degrades due to frequent cache line invalidations
Solution Approach 1:
The patent segments the cache line into individual variable-level tracking units. Instead of invalidating entire cache lines, the system tracks and invalidates only specific variables within cache lines that are actually modified, reducing unnecessary invalidations while maintaining data consistency for accessed variables.
Solution Approach 2:
The patent implements a feedback mechanism through instrumentation that monitors memory access patterns and cache invalidation events. This feedback enables the system to distinguish between true sharing (necessary invalidations) and false sharing (unnecessary invalidations), allowing selective optimization to maintain reliability while improving productivity.
2Measurement precision
If instrumentation is added to track memory access addresses and types of all global and heap variables, then false sharing detection accuracy is improved, but device complexity and memory overhead increase
Solution Approach 1:
The patent applies local quality by instrumenting only specific variables that are likely to cause false sharing based on their access patterns and locations, rather than uniformly instrumenting all global and heap variables. This selective instrumentation reduces complexity while maintaining detection accuracy for critical variables.
Solution Approach 2:
The patent uses partial action by implementing threshold-based tracking that monitors only a subset of memory accesses above certain thresholds, rather than tracking every single access. This approach provides sufficient detection accuracy while significantly reducing the overhead of complete instrumentation.
3Productivity
If optimization passes are performed on source code before adding instrumentation, then code efficiency is improved, but detection capability may be compromised due to code transformations
Solution Approach 1:
The patent performs optimization passes as a preliminary action before adding instrumentation. This sequence allows the code to be optimized for efficiency first, and then instrumentation is added to the optimized code, ensuring both productivity improvement and detection capability are achieved without conflict.
Solution Approach 2:
The patent uses an intermediary approach by performing optimizations at the intermediate representation level during compilation, then adding instrumentation that works with the optimized code structure. This intermediary optimization layer maintains detection capability while improving code efficiency.
Data Source
AI summary
In one embodiment, a method of false sharing detection includes performing, by a device, a plurality of optimization passes on source code, to produce optimized source code and receiving, by the device, selection criteria, The method also includes adding instrumentation to the optimized source code, by the device, after performing the plurality of optimization passes, to produce an instrumented code, where the instrumentation is configured to track memory access addresses and access types of global variables and heap variables in accordance with the selection criteria.